FUSB3317

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10

USB Power Delivery Support

Figure 7. USB−PD Communication Stack

Physical Layer

Protocol

Policy Engine

Device Policy

Manager

CC

Physical Layer

Protocol

Policy Engine

Device Policy

Manager

Provider

Consumer

USB Power Delivery (PD) provides a way for a Source

and Sink to negotiate output power settings, allowing for

increased power delivery up to 100 W for Standard Power

Range (SPR). USB PD uses the CC signal that is passed

through the cable to provide the link between the Source and

the Sink to send messages and commands. The

communications stack consists of Physical, Protocol, Policy

Engine and Device Policy Manager layers as shown in

Figure 7 where each layer in the FUSB3317 talks to its

corresponding layer in the Sink device.

The Physical (PHY) Layer handles both the transmission

and reception of the bits on the CC signal. All data is first

encoded using a 4b5b line code and then transmitted across

the CC signal using Biphase Mark Coding (BMC). A

32

*bit CRC is also used to protect the data integrity of the

data payload.

The Protocol Layer defines how USB PD messages are

constructed and used between a Source device and a Sink

device. All USB PD messages must follow a strict packet

definition and may also include timing requirements based

on the type of message. The Protocol Layer is responsible

for verifying the timing parameters and handling any

communication errors as they arise.

The Policy Engine (PE) is responsible for executing the

device Local Policy to control its power delivery behavior.

The Policy Engine defines a set of message sequences that

must be followed for proper operation. All power

negotiations are handled by the Policy Engine.

The Device Policy Manager (DPM) is responsible for

overseeing the power supply and managing changes to the

Local Policy, including handling of alert and fault

conditions. It is also responsible for managing VCONN and

the Discover Identity messaging to determine the full

capabilities of the cabling.

FUSB3317 consists of all four PHY, Protocol, PE and

DPM layers to fully implement a compliant PD Source fully

in hardware.

USB PD Power Advertisement

The USB PD specification defines Power Data Objects

(PDO) and Augmented Power Data Objects (APDO) as a

way for the Source device to advertise it’s power

capabilities. PDO’s describe well

*regulated fixed voltage

supplies while APDO Programmable Power Supply (PPS)

describe a power supply whose output voltage can be

adjusted over the advertised voltage range. A Source can

advertise a combination of PDOs and APDOs, up to a

maximum of 7 total Data Objects for SPR. In order to

provide a consistent experience across the Source devices

with the same PD Power (PDP) rating, a set of power rules

are contained within the PD specification. The power rules

provide a set of minimum requirements (PDOs and APDOs)

that must be met for a Source device based on the advertised

PDP.

The FUSB3317 can be configured to meet a variety of

different PDP power advertisements, depending on the

application requirements. The default power for the

FUSB3317 is the standard 60 W option as shown in Table 1.

Table 1. FUSB3317 DEFAULT PDOs AND APDOs

[A]PDO Power

Data Object

Output

Voltage

Max Current

w/3 A Cable

Current

Mode

PDO1

5 V

3.6 A

OCP

PDO2

9 V

3.6 A

OCP

PDO3

15 V

3.6 A

OCP

PDO4

20 V

3.6 A

OCP

APDO1

3.3 V ~ 21 V

3 A

CL or CC

Constant Voltage Control

In order to regulate adaptive output voltages, the constant

voltage control (CV) is implemented. The output voltage is

sensed through an external resistor divider. The sensed

output voltage is connected to the VFB pin, and it is input the

non

*inverting input terminal of the internal operational

amplifier. The inverting input terminal is connected to the

according to the requested output voltage. The amplifier and

an internal switch operate as a shunt regulator, and the output

of the shunt regulator is connected to the CATH pin. To

compensate output voltage regulation, typically, two

capacitors and one resistor are connected between CATH

and VFB pins as Figure 8. The output voltage can be derived

as calculated by the Equation 1, and the ratio of the resistor

divider is 10. The reference (VCVR) for the output voltage

is generated by a 10

*bit DAC. The minimum resolution is

20 mV to meet PD compliance for PPS.

(eq. 1)