PCF8545ATT datasheet(40/68 Pages) NXP

40 / 68 page

NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

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S 0 1 1 1 0

target address

readout byte

A P

R/W = 1

acknowledge

from controller

(1)

1. From PCF8545.

Figure 31. I2C-bus protocol read mode

In the unlikely case that the chip has entered the internal test mode, detection of this

state is possible by using the modified status read-out detailed in Table 28. The read out

value is modified to indicate that the chip has entered an internal test mode.

Bit

Symbol

Value

Description

7 to 1

1111 000

fixed value

read back value is 1111 0000

read back value is 1111 0001

Table 28. Modified status read out value

EMC detection

The PCF8545 is ruggedized against EMC susceptibility; however it is not possible to

cover all cases. To detect if a severe EMC event has occurred, it is possible to check the

responsiveness of the device by reading its register.

8.3 SPI-bus interface

Data transfer to the device is made via a 3 line SPI-bus (see Table 29). There is no

output data line. The SPI-bus is initialized whenever the chip enable line pin CE is

inactive.

Symbol

Function

Description

chip enable input[1]; active LOW

when HIGH, the interface is reset

SCL

serial clock input

input may be higher than VDD

SDI

serial data input

input may be higher than VDD; input data is

sampled on the rising edge of SCL

Table 29. Serial interface

[1]

The chip enable must not be wired permanently LOW.

8.3.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a

byte with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal CE. The first byte

transmitted is the subaddress byte.

PCF8545

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 4 October 2021

40 / 68

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