PCF8545ATT datasheet(35/68 Pages) NXP

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NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

0 1 2 3 4 5 6 7

35 36 37 38 39

MSB

LSB

Transmitted data byte

Display RAM columns/segment outputs (S)

Columns

Display RAM rows/

backplane outputs

(BP)

Rows

013aaa459

Figure 24. Display RAM filling order in 1:8 multiplex drive mode

There are no boundary conditions in 1:8 multiplex drive mode.

8 Bus interfaces

8.1 Control byte and register selection

After initiating the communication over the bus and sending the target address (I2C-bus,

see Section 8.2) or subaddress (SPI-bus, see Section 8.3), a control byte follows. The

purpose of this byte is to indicate both, the content for the following data bytes (RAM, or

command) and to indicate that more control bytes will follow.

Typical sequences could be:

• target address/subaddress - control byte - command byte - command byte - command

byte - end

• target address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end

• target address/subaddress - control byte - command byte - control byte - RAM byte -

end

In this way, it is possible to send a mixture of RAM and command data in one access or

alternatively, to send just one type of data in one access.

Bit

Symbol

Value

Description

continue bit

last control byte

control bytes continue

command register

6 to 5

RS[1:0]

RAM data

Table 24. Control byte description

PCF8545

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 4 October 2021

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