STM32L031C6 datasheet(26/126 Pages) STMICROELECTRONICS

26 / 126 page

Functional overview

STM32L031x4/6

26/126

DS10668 Rev 6

3.8

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 26 edge detector lines used to generate

interrupt/event requests. Each line can be individually configured to select the trigger event

(rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 38 GPIOs can be connected

to the 16 configurable interrupt/event lines. The 10 other lines are connected to PVD, RTC,

USART, I2C, LPUART, LPTIMER or comparator events.

3.9

Memories

The STM32L031x4/6 devices have the following features:

•

8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states. With the enhanced bus matrix, operating the RAM does not lead to any

performance penalty during accesses to the system bus (AHB and APB buses).

•

The non-volatile memory is divided into three arrays:

–

16 or 32 Kbytes of embedded Flash program memory

–

1 Kbytes of data EEPROM

–

Information block containing 32 user and factory options bytes plus 4 Kbytes of

system memory

The user options bytes are used to write-protect or read-out protect the memory (with 4-

Kbyte granularity) and/or readout-protect the whole memory with the following options:

•

Level 0: no protection

•

Level 1: memory readout protected.

The Flash memory cannot be read from or written to if either debug features are

connected or boot in RAM is selected

•

Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in

RAM selection disabled (debugline fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.10

Direct memory access (DMA)

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management, avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger

support for each channel. Configuration is done by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, LPUART,

general-purpose timers, and ADC.

STM32L031C6 датащи(PDF) 26 Page - STMicroelectronics

STM32L031C6 датащи(HTML) 26 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL