STM32WB10CC datasheet(51/110 Pages) STMICROELECTRONICS

номер детали	STM32WB10CC

подробное описание детали	Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 radio solution

PDF	110 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

Logo

51 / 110 page

DS13259 Rev 2

51/110

STM32WB10CC

Memory mapping

The STM32WB10CC devices feature a single physical address space that can be accessed

by the application processor and by the RF subsystem.

A part of the Flash memory and of the SRAM2a and SRAM2b is made secure, exclusively

accessible by the CPU2, protected against execution, read and write from CPU1 and DMA.

In case of shared resources the SW has to implement arbitration mechanism to avoid

access conflicts. This happens for peripherals Reset and clock controller (RCC), Power

controller (PWC), EXTI and Flash memory interface, and can be implemented using the

built-in semaphore block (HSEM).

By default the RF subsystem and the CPU2 operate in secure mode. This implies that part

of the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and

by the CPU2. In this case the Host processor (CPU1) has no access to these resources.

The detailed memory map and the peripheral mapping of the STM32WB10CC can be found

in the reference manual RM0478.

STM32WB10CC датащи(PDF) 51 Page - STMicroelectronics