3.3

Recommended PCB Layouts

3.3.1

Recommended PCB Layout for 32-Pin QFN 5 mm x 5 mm

The following figures show the PCB layout pattern for PD69200. The units are in mm.

Figure 3-2. Top Layer Copper PCB Layout

0.96

0.37

0.50

3.50

3.87

5.85

Figure 3-3. PD69200 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array

1.45

3.30

1.45

0.66

0.23

0.50

3.73

5.38

4.06

The contract manufacturer has latitude to modify the solder paste stencil for manufacturability reasons. The solder

paste stencil covers 65% to 80% of the thermal pad and must not allow solder to be applied to the thermal vias under

the QFN package using any method they deem appropriate. Any design should be subject to system validation and

qualification prior to commitment to mass production of field deployment. Use a 5 mil stencil.

PD69200

Pin Descriptions

Datasheet

DS00003460A-page 12