3.2

Pin Details

The following tables describe the functional pin descriptions of the PD69200 device.

Table 3-1. PD69200 Pin Description

Number

Designation

Type

Description

1

Reserved

OUT

Reserved UART - Leave Open

2

Reserved

IN

Reserved UART - Pull up to 3.3 V via 10K

3

ESPI_xCS

OUT

ESPI Bus to PoE Manager. SPI chip select.

Pull-up required. See AN3361 for pin

connection requirements. (Active Low)

4

ESPI_SCK

OUT

ESPI Bus to PoE Manager. SPI clock output to

PD6920x, and LED stream clock output, set to

1 MHz.

5

ESPI_MOSI

OUT

ESPI Bus to PoE Manager. SPI Master Out

Slave In. SPI packets are transmitted on this

line.

6

ESPI_MISO

IN

ESPI Bus to PoE Manager. SPI Master In

Slave Out. SPI packets are received on this

line.

7

VDDA

Supply

Main Supply 3.3 V

8

VSSA

GND

Ground

9

Reserved

Analog_IN

Reserved Analog_IN. Connect to 3.3 V.

10

SWD_CLK

Leave Open

11

UART0_RXx

IN

UART receive from host. 15-byte protocol

commands are received on this line. The baud

rate is set to 19,200 bps. A pull up is required.

See AN3361 for details.

12

UART0_TX

OUT

UART transmit to host. 15-byte protocol reply/

telemetry is transmitted on this line. The baud

rate is set to 19,200 bps.

13

SWD_DIO

Leave Open

14

Reserved

Analog_IN

Reserved Analog_IN. Connect to 3.3 V or GND

through 10 kΩ.

15

VDD

Supply

Main Supply 3.3 V

16

VSSD

GND

Ground

17

Reserved

Oscillator

Reserved – Oscillator input – Leave open

18

Reserved

Oscillator

Reserved – Oscillator output – Leave open

19

xRESET

IN/OUT

Host Reset input. This pin is active low. The

controller can generate self-reset. In this case,

the xRESET pin is driven low by the controller

for about 100 μs. See AN3361 for pin

connection requirements.

PD69200

Pin Descriptions

Datasheet

DS00003460A-page 10