LTC4232 datasheet(15/18 Pages) AD

15 / 18 page

LT4200

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

=R4•

VUV

1.235V

−1

⎛

⎝⎜

⎞

⎠⎟ =

140k

(13)

=R6•

VPG

1.235V

−1

⎛

⎝⎜

⎞

⎠⎟ =

150k

(14)

The final schematic in Figure 5 results in very few external

components. The pull-up resistor, R7, connects to the PG

pin while the 20k (RMON) converts the IMON current to a

voltage at a ratio given by Equation 15.

VIMON = 2[µA/A] • 20k • IOUT = 0.04[V/A] • IOUT

(15)

In addition there is a 1µF bypass (C1) on the INTVCC

pin and note the connection between SENSE+ to VDD

(Pin 32 to Pin 22).

Layout Considerations

In hot swap applications where load currents can be 50A,

narrow PCB tracks exhibit more resistance than wider

tracks and operate at elevated temperatures. The mini-

mum trace width requirement for 2oz copper foil is 0.01"

per amp to make sure the trace stays at a reasonable tem-

perature. Using 0.02" per amp or wider is recommended.

Note that 2oz copper exhibits a sheet resistance of about

0.25mΩ/square. Small resistances add up quickly in high

current applications.

The SENSE+ pin can be connected to the middle of the

wide VDD trace near pin 26 to provide Kelvin sensing for

VDD (see Figure 6). Make sure to minimize the solder joint

resistance at these VDD pins by applying solder along the

whole length of the VDD bar that connects pin 22 to 30.

High solder joint resistance will add error to the IMON

gain and ILIM(TH) accuracy.

During normal operation, the power dissipated in the

MOSFET could be as high as 3W. To remove this heat,

solder the SENSE–, exposed pad to a copper trace that

contains vias underneath the pad. The OUT pins conduct

substantial heat from the MOSFET. Connect all the OUT

pins to a plane of 2oz copper. Since the trace that connects

OUT pins must accommodate high current, this area of

copper is usually present. It is also important to put C1,

the bypass capacitor for the INTVCC pin, as close as pos-

sible between INTVCC and GND.

OUT

VDD

SENSE–

TRACE FOR VDD

KELVIN SENSING

ON LOWER (OR INTERIOR)

LAYER OFPCB

MULTIPLE VIA TO CONNECT

SENSE– TO BIG COPPER

PLANES ON OTHER

LAYERS OFPCB

GND

4200 F06

GND

Figure 6. Recommended Layout

Thermal Considerations

If the LT4200 operates near its maximum load current of

50A, the junction temperature can rise to a level near the

thermal shutdown temperature if insufficient heat sink-

ing is used. Always maximize the PCB copper area and

thickness connected to the SENSE–, OUT and VDD pins.

The VDD and OUT pins require a wide copper trace to

carry the 50A current which will also help to conduct the

heat away from the LT4200. The SENSE– exposed pad,

although not carrying any current, should be as big as

possible to help in the heat dissipation of the internal

MOSFET. As shown in Figure 6, the SENSE– exposed pad

can be connected through via to the other layers of the

PCB with large copper planes. The size and thickness of

these copper planes will affect the junction temperature

of the LT4200. For example, the temperature rise is 38°C

at 50A with an 8-layer PCB (2oz copper for top/bottom

PCB layers with the rest 1oz thick) and with a large cop-

per area of 17 inch square connected to SENSE– on the

middle layers. If we reduce the copper area on the middle

layers to 1-inch square, the temperature rise increases by

another 20°C at 50A.

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