LTC4232 datasheet(10/18 Pages) AD

10 / 18 page

LT4200

Rev. 0

For more information www.analog.com

The typical LT4200 application is in a high availability

system that uses a positive voltage supply to distribute

power to individual cards. The application circuit is shown

in Figure 1. External component selection is discussed in

detail in the following sections.

Turn-On Sequence

Several conditions must be present before the internal

pass MOSFET can be turned on. First, the supply VDD

must exceed its undervoltage lockout level. Next, the

internally generated supply INTVCC must cross its 2.65V

undervoltage threshold. This generates a 25µs power-on-

reset pulse which clears the fault register and initializes

internal latches.

APPLICATIONS INFORMATION

After the power-on-reset pulse, the UV and OV pins must

indicate that the input voltage is within the acceptable

range. All of these conditions must be satisfied for a dura-

tion of 48ms to ensure that any contact bounce during

the insertion has ended.

The inrush current into the load capacitor, CL, is controlled

by limiting the dv/dt on the MOSFET’s GATE pin. The same

dv/dt will be generated on the OUTPUT pin. Figure 2 illus-

trate the turn-on ramp rate without CGATE. This internal

gate slope of 0.35V/ms will result in an inrush current

defined by Equation 1.

IINRUSH =CL • 0.35[V/ms]

(1)

ADC

226k

1µF

20k

12V

4200 F01

0.1µF

*TVS Z1: DIODES INC. SMCJ15A

1000µF

VOUT

12V

20A

VDD

Z1*

OUT

GND

IMON

RSET

20k

RMON

20k

ISET

CGATE

0.1µF

RGATE

100k

GATE

LT4200

INTVCC

TIMER

SENSE+

FLT#

140k

20k

CCOMP

3.3nF

10k

UV = 9.88V

OV = 15.2V

PG = 10.5V

20k

150k

Figure 1. 20A, 12V Card Resident Application, Auto-Retry

SLOPE = 0.35[V/ms]

GATE

OUT

VDD + 12V

VDD

4200 F02

Figure 2. Supply Turn-On without CGATE

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