(4)

Ports 1 and 2 can each be used to support multiple source options for a given product (for example AFE and HDMI). To do so, the

data bus from both source components must be connected to the same port pins (1 or 2) and control given to the DLPC4420 device

to tri-state the "inactive" source. Tying them together like this causes some signal degradation due to reflections on the tri-stated path.

Given the clock is the most critical signal, three Port clocks (1,2,and 3) are provided to provide an option to improve the signal integrity.

(5)

Ports 1 and 2 can be used separately as two 30-bit ports, or can be combined into one 60-bit port (typically for high data rate sources)

for transmission of two pixels per clock.

(6)

The A, B, C input data channels of Ports 1 and 2 can be internally re-configured/ re-mapped for optimum board layout.

(7)

Sources feeding less than the full 10-bits per color component channel have to be MSB justified when connected to the DLPC4420

controller and the LSBs tied off to zero. For example an 8-bit per color input has to be connected to bits 9:2 of the corresponding A, B,

C input channel.

(8)

GPIO signals must be configured by software for input, output, bidirectional, or open-drain. Some GPIOs have one or more alternate

use modes, which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate

function connected to these GPIO pins with the exception of general-purpose clocks and PWM generation, are reset. An external

pullup to the 3.3V supply is required for each signal configured as open-drain. External pullup or pulldown resistors may be required to

ensure stable operation before software is able to configure these ports.

DLPC4420

DLPS222 – DECEMBER 2021

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