DLPC4420ZPC datasheet(35/49 Pages) TI

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voltage for detecting the loss of power, as well as the reaction time to respond to a low voltage condition is not

critical for POSENSE as PWRGOOD is used for this purpose. As such, PWRGOOD has critical requirements in

these areas.

9.4 System Environment and Defaults

9.4.1 DLPC4420 System Power-Up and Reset Default Conditions

Following system power-up, the DLPC4420 controller performs a power-up initialization routine that defaults the

device to a normal power mode, in which ARM9-related clocks are enabled at their full rate and associated

resets are released. Most other clocks default to disabled state with associated resets asserted until released

by the processor. In addition, the default for system power gating enables all power. These same defaults are

also applied as part of all system reset events (Watch Dog timer timeout etc.) that occur without removing or

cycling power, with the possible exception of power for the LVDS I/O and internal DRAM. For an extended reset

condition, the OEM is expected to place the controller in Low Power mode prior to reset, in which case the 1.8V

power for the LVDS I/O and internal DRAM are disabled. When this reset is released, the 1.8V power does not

get enabled until the ARM9 has been initialized and is executing the system initialization routines.

Following power-up or system reset initialization, the ARM9 boots from an external flash memory after which it

enables the 1.8V power (from the DLPA100), enables the rest of the controller clocks, and initializes the internal

DRAM. Once system initialization is complete the Application software determines if and when to enter low

power mode.

9.4.2 1.1V System Power

The DLPC4420 controller can support a low cost power delivery system with a single 1.1V power source derived

from a switching regulator. To enable this approach, appropriate filtering must be provided for the 1.1V power

pins of the PLLs.

9.4.3 1.8V System Power

It is recommended that the DLPC4420 controller power delivery system provides two independent 1.8V power

sources. One of the 1.8V power sources is used to supply 1.8V power to the controller LVDS I/O and internal

DRAM. Power for these functions is fed from a common source which is recommended to be a linear regulator.

The second 1.8V power source is used (along with appropriate filtering as discussed in the PCB layout

guidelines for internal ASIC PLL power section of this document) to supply all of the DLPC4420 controller

internal PLLs. In order to keep this power as clean as possible, a dedicated linear regulator for the 1.8V power to

the PLLs is recommended.

9.4.4 3.3V System Power

The DLPC4420 controller can support a low cost power delivery system with a single 3.3V power source derived

from a switching regulator. This 3.3V source supplies power to all LVTTL I/O and the Crystal Oscillator cell. The

3.3V power must remain active in all power modes for which 1.1V core power is applied.

9.4.5 Power Good (PWRGOOD) Support

The PWRGOOD signal is defined as an early warning signal that alerts the DLPC4420 controller a specified

amount of time before the DC supply voltages drop below specifications, which allows the controller to park the

DMD and to place the system into reset, ensuring the integrity of future operation. For practical reasons, it is

recommended that the monitor sensing PWRGOOD be on the input side of supply regulators.

9.4.6 5V Tolerant Support

With the exception of USB_DAT, the DLPC4420 controller does not support any other 5V tolerant I/Os. However,

note that source signals ALF_HSYNC, ALF_VSYNC and I2C typically have 5V requirements and special

measures must be taken to support them. Also, 5V to 3.3V level shifter is recommended.

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DLPC4420

DLPS222 – DECEMBER 2021

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