DLPC4420ZPC datasheet(40/49 Pages) TI

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Table 10-1. General PCB Routing (Applies to All Corresponding PCB Signals)

PARAMETER

APPLICATION

SINGLE-ENDED SIGNAL

DIFFERENTIAL PAIRS

UNIT

Line width (W)(1)

Escape Routing in Ball

Field

4 (0.1)

mil (mm)

PCB Etch Data or Control

7 (0.18)

4.25 (0.11)

mil (mm)

PCB Etch Clocks

7 (0.18)

4.25 (0.11)

mil (mm)

Minimum Line spacing to

other signals (S)

Escape Routing in Ball

Field

4 (0.1)

mil (mm)

PCB Etch Data or Control

10 (0.25)

20 (0.51)

mil (mm)

PCB Etch Clocks

20 (0.51)

mil (mm)

(1)

Line width is expected to be adjusted to achieve impedance requirements

Table 10-2. DMD I/F, PCB Interconnect Length Matching Requirements

SIGNAL GROUP LENGTH MATCHING

I/F

SIGNAL GROUP

REFERENCE SIGNAL

MAX MISMATCH

UNIT

DMD (LVDS)

SCA_P,SCA_N,

DDA_P(15:0),

DDA_N(15:0)

DCKA_P, DCKA_N

+/-150 (+/-3.81)

mil (mm)

DMD (LVDS)

SCB_P,SCB_N,

DDB_P(15:0),

DDB_N(15:0)

DCKB_P, DCKB_N

+/-150 (+/-3.81)

mil (mm)

Number of layer changes:

• Single ended signals: Minimize

• Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair

typically does not change layers.

Termination requirements:

• DMD Interface - None, the DMD receiver is differentially terminated to 100 ohms internally

Connector (DMD-LVDS I/F bus only) - High Speed Connectors that meet the following requirements must be

used:

● Differential Crosstalk

<5 %

● Differential Impedance

75-125 ohms

Routing requirements for right angle connectors:

When using right angle connectors, P-N pairs have to be routed in same row to minimize delay mismatch and

propagation delay difference for each row has to be accounted for on associated PCB etch lengths.

DLPC4420

DLPS222 – DECEMBER 2021

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