STSPIN32G4 datasheet(26/48 Pages) STMICROELECTRONICS

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Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read

and write from third parties.

•

Securable memory area: a part of the Flash memory can be configured by option bytes to be securable.

At startup, a BOOT0 pin (or nBOOT0 option bit) and an nBOOT1 option bit are used to select one of three boot

options:

•

Boot from user Flash

•

Boot from system memory

•

Boot from embedded SRAM

The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit depending on the value of

a user nBOOT_SEL option bit to free the GPIO pad if needed.

The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C,

SPI, and USB through the DFU (device firmware upgrade).

5.3.2

Power management

VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power

management and internal clocks. It is provided externally through the VDD pins.

VDDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational

amplifiers, and comparators. The VDDA voltage level is independent from the VDD voltage and should preferably

be connected to VDD when these peripherals are not used.

VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch)

when VDD is not present.

During power-up and power-down, the following power sequence is required:

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When VDD is below 1 V, then VDDA supply must remain below VDD + 300 mV

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When VDD is above 1 V, all power supplies became independent.

During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided

to the MCU remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time

constants during the power-down transient phase.

VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference

buffer when enabled.

The device has an integrated ultra-low-power Brown-Out reset (BOR) active in all modes (except for Shutdown

mode). The BOR ensures proper operation of the device after power-on and during power-down. The device

remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need

for an external reset circuit. The lowest BOR level is 1.71 V at power-on, and other higher thresholds can be

selected through option bytes.

The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply

and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold

and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a peripheral voltage monitor which compares the independent supply voltages

VDDA, with a fixed threshold in order to ensure that the peripheral is in its functional supply range.

The MCU supports three low-power modes to achieve the best compromise between low-power consumption,

short start-up time and available wake-up sources:

•

Sleep mode: only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when

an interrupt/event occurs.

•

Low-power run mode: this mode is achieved with VCORE supplied by the low-power regulator to minimize

the regulator's operating current.

•

Stop mode: the device achieves the lowest power consumption while retaining the SRAM and register

contents.

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Standby mode: is used to achieve the lowest power consumption with Brown-Out reset, BOR. The device

exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin,

configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a

failure is detected on LSE (CSS on LSE).

STSPIN32G4

Microcontroller unit

DS13630 - Rev 1

page 26/48

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