STSPIN32G4 datasheet(25/48 Pages) STMICROELECTRONICS

25 / 48 page

5.2.6

Undervoltage protection

The device provides undervoltage lockout (UVLO) protections on the supply voltages of the gate drivers. When

in UVLO condition, the gate drivers keep their outputs low with the maximum current capability available. During

power-up, the device leaves the UVLO condition when the respective supply voltage rises above the turn-on

threshold. When the supply voltage is below the on-threshold voltage of a hysteresis, the UVLO condition is set.

Table 12. UVLO protection management

Block

VCC UVLO

VBOx UVLO

HS1, HS2, HS3 output

LOW(1)

LOW(1)(2)

LS1, LS2, LS3 output

LOW(1)

READY open-drain output

LOW(3)

1. The N-channel of the gate driver is turned ON with all the available supply voltage, refer to Figure 16.

2. Each high-side gate driver provides independent UVLO protection (e.g. UVLO on BOOT1 causes the HS1 to turn off only).

3. If VCC_UVLO_RDY is set.

5.3

Microcontroller unit

The integrated MCU is the STM32G431VBx3 with the following main characteristics:

•

Core: ARM® Cortex®-M4 32-bit CPU + FPU, frequency up to 170 MHz

•

32 kB of SRAM, 128 kB of Flash memory

•

2 x ADCs 16-bit resolution and 0.2 µs sampling time

•

4 x 12-bit DAC channels

•

4 x fast rail-to-rail comparators

•

3 x rail-to-rail operational amplifiers

•

Full set of interfaces:

•

CAN, UART, I2C, SPI

For more details refer to the STM32G431VBx3 datasheet on www.st.com

5.3.1

Memories and boot mode

The device has the following features:

•

32 kB of embedded SRAM

•

The non-volatile memory is dived into two arrays:

–

128 kB of embedded Flash memory for storing programs and data

–

Option bytes

The Flash memory embeds the error correction code (ECC) feature supporting:

•

Single error detection and correction

•

Double error detection

•

The address of the ECC fail can be read in the ECC register

•

1 kB (128 double word) OTP (one-time programmable) bytes for user data. The OTP area is available in

Bank 1 only. The OTP data cannot be erased and can be written only once.

Flexible protections can be configured thanks to the option bytes:

•

Readout-protection (RDP) to protect the whole memory with the following options:

–

Level 0: no readout protection

–

Level 1: memory readout protection; the Flash memory cannot be read from or written to if either the

debug features are connected or the boot in RAM or bootloader are selected.

–

Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial wire), the boot in RAM

and the bootloader selection are disabled (JTAG fuse). This selection is irreversible.

•

Write protection (WRP): the protected area is protected against erasing and programming.

STSPIN32G4

Microcontroller unit

DS13630 - Rev 1

page 25/48

STSPIN32G4 датащи(PDF) 25 Page - STMicroelectronics

STSPIN32G4 датащи(HTML) 25 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL