ES9219 datasheet(44/67 Pages) ESS

44 / 67 page

ES9219 Datasheet

February 27, 2020

CONFIDENTIAL ADVANCE INFORMATION 1.0.4

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[7:6]

[5:3]

[2]

[1:0]

Mnemonic

INVERT_GPIO

RESERVED

AUTO_CLK_GEAR

MAX_CLK_GEAR

Bits

Mnemonic

Description

[7:6]

INVERT_GPIO

Allows each GPIO output to be inverted independently.

2’b00: Normal GPIO operation (default).

2’b01: Invert GPIO1 output only.

2’b10: Invert GPIO2 output only.

2’b11: Invert both GPIO outputs.

[5:3]

RESERVED

[2]

AUTO_CLK_GEAR

Allows the digital core to automatically adjust the clock gear setting by counting the number of MCLK

pulses per 1fs.

If the number of MCLK pulses exceeds a threshold, then the clock gear will decrease (get faster) and if the

number of MCLK pulses is below a threshold then the clock gear will increase (get slower).

This allows the Sabre to automatically save power when running at lower sample rates.

1’b0: Automatic clock gearing is disabled (default).

1’b1: Automatic clock gearing is enabled.

See Register 49-51: Automatic Clock Gearing Thresholds for threshold setting

[1:0]

MAX_CLK_GEAR

Selects the maximum amount of clock gearing that the automatic clock gearing circuitry can implement.

This is useful when running at slow clock rates where a clock gear could slow the MCLK down below the

I2C programming constraints.

2’b00: Sets MCLK/1 as the maximum clock gearing ratio (effectively disabling the automatic clock gearing)

(default).

2’b01: Sets MCLK/2 as the maximum clock gearing ratio.

2’b10: Sets MCLK/4 as the maximum clock gearing ratio.

2’b11: Sets MCLK/8 as the maximum clock gearing ratio.

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[15:14]

[13:12]

[11:0]

Mnemonic

CP_CLK_SEL

CP_CLK_EN

CP_CLK_DIV

Bits

Mnemonic

Description

[15:14]

CP_CLK_SEL

Selects which clock will be used as the reference clock for the charge pump clock.

2’b00: Use MCLK as the reference clock (default).

2’b01: Use 128*fs as the reference clock.

2’b10: Use 64*fs as the reference clock.

2’b11: Use 1*fs as the reference clock.

[13:12]

CP_CLK_EN

Sets the state of the charge pump clock.

2’b00: Tristate output (default).

2’b01: Tied to GND.

2’b10: Tied to DVDD.

2’b11: cp_clk_sel/ cp_clk_div.

[11:0]

CP_CLK_DIV

Sets the divider ratio for the charge pump clock. F_CLK is the frequency of the clock selected by cp_clk_sel.

�� = ��

��(��

��

+1) ∗ 2

ES9219 датащи(PDF) 44 Page - ESS Technology,Inc

ES9219 датащи(HTML) 44 Page - ESS Technology,Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

датащи скачать

ссылки URL