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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ES9219 датащи(PDF) 28 Page - ESS Technology,Inc |
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ES9219 датащи(HTML) 28 Page - ESS Technology,Inc |
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28 / 67 page  ES9219 Datasheet February 27, 2020 CONFIDENTIAL ADVANCE INFORMATION 1.0.4 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801 28 Start Start Start Stop Figure 6. I2C Control Interface Parameter Symbol CLK Constraint Standard-Mode Fast-Mode Unit MIN MAX MIN MAX SCL Clock Frequency fSCL < CLK/20 0 100 0 400 kHz START condition hold time tHD,STA 4.0 - 0.6 - s LOW period of SCL tLOW >10/CLK 4.7 - 1.3 - s HIGH period of SCL (>10/CLK) tHIGH >10/CLK 4.0 - 0.6 - s START condition setup time (repeat) tSU,STA 4.7 - 0.6 - s SDA hold time from SCL falling - All except NACK read - NACK read only tHD,DAT 0 2/CLK - 0 2/CLK - s s SDA setup time from SCL rising tSU,DAT 250 - 100 - ns Rise time of SDA and SCL tr - 1000 300 ns Fall time of SDA and SCL tf - 300 300 ns STOP condition setup time tSU,STO 4 - 0.6 - s Bus free time between transmissions tBUF 4.7 - 1.3 - s Capacitive load for each bus line Cb - 400 - 400 pF The I2C master clock is affected by the clock gearing. If the auto clock gearing lowers CLK by too much it can cause I2C transactions to fail. See Register 29: GPIO CONFIGURATION AND AUTO CLOCK GEAR for clock gearing options. CLK Requirement t(SCL high) >=10*t(Clock Gear(CLK)) t(SCL low) >=10*t(Clock Gear(CLK)) The system must ensure this condition can still be met when enabling automatic clock gearing. If the criterion cannot be met for all clock gear settings, then the clock gearing must be limited using Register 29: GPIO CONFIGURATION AND AUTO CLOCK GEAR. |
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