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ES9219 датащи(PDF) 29 Page - ESS Technology,Inc

номер детали ES9219
подробное описание детали  32-bit Stereo Low Power DAC with Headphone Amplifier, Analog Volume Control, and Output Switch
PDF  67 Pages
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производитель  ESS [ESS Technology,Inc]
домашняя страница  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9219 датащи(HTML) 29 Page - ESS Technology,Inc

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ES9219 Datasheet
CONFIDENTIAL ADVANCE INFORMATION 1.0.4
February 27, 2020
29
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801
XIN/MCLK Timing
t
MCH
t
MCL
t
MCY
MCLK
t
MCH
t
MCL
t
MCY
MCLK
Figure 7. Clock Timing
Parameter
Symbol
Min
Max
Unit
MCLK pulse width high
TMCH
9.0
90
ns
MCLK pulse width low
TMCL
9.0
90
ns
MCLK cycle time
TMCY
20
200
ns
MCLK duty cycle
45:55
55:45
5������������ ≤ ���������������� ≤ 50������������
Audio Interface Timing
L
t
DCH
t
DCL
t
DCY
DATA_CLK
t
DH
t
DS
DATA[8:1]
Valid
Invalid
Valid
t
DCH
t
DCL
t
DCY
DATA_CLK
t
DH
t
DS
DATA[8:1]
Valid
Invalid
Valid
DATA_CLK
DATA[2:1]
Parameter
Symbol
Min
Max
Unit
DATA_CLK pulse width high
tDCH
9.0
ns
DATA_CLK pulse width low
tDCL
9.0
ns
DATA_CLK cycle time
tDCY
20
ns
DATA_CLK duty cycle
45:55
55:45
DATA set-up time to DATA_CLK rising edge
tDS
4.1
ns
DATA hold time to DATA_CLK rising edge
tDH
2
ns
Figure 8. Audio Interface Timing
Notes:
•
Audio data on DATA[2:1] are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time requirements relative to the
rising edge of DATA_CLK
•
For DSD Phase mode, the normal data (D0, D1, D2) must satisfy the setup and hold time requirements relative to the rising edge of DATA_CLK.
The complimentary data (D0, D1, etc.) will be ignored.



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