ES9219 datasheet(19/67 Pages) ESS

19 / 67 page

ES9219 Datasheet

CONFIDENTIAL ADVANCE INFORMATION 1.0.4

February 27, 2020

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

Overcurrent Protection

Overcurrent Protection (OCP) protects the amplifier output stage by independently sensing the positive and negative output current on the OUT_R

and OUT_L pins. Once the current exceeds a built-in threshold for a cumulative user programmable timeout period, an OCP event will be triggered

and both DAC channels will be muted.

OCP must be enabled and configured using oc_sd_en and oc_sd_gain in Register 11: OVERCURRENT PROTECTION; it is disabled by default.

When an overcurrent event is triggered, oc_sd_mute Register 72: READ INPUT SELECTION AND AUTOMUTE STATUS will be set and latched to

indicate which channel triggered the event.

OCP does not automatically reset when the overcurrent condition is removed. After an OCP event occurs, the state of the OCP circuit needs to be

manually cleared. This is accomplished by toggling OCP disabled-enabled with oc_sd_en.

Once enabled, the OCP status can be monitored in one of two ways:

1. Poll the oc_sd_mute flags in Register 72: READ INPUT SELECTION AND AUTOMUTE STATUS

2. Configure Register 8: GPIO1-2 CONFIGURATION to set the desired GPIO pin to Interrupt mode and set Register 33: INTERRUPT MASK

appropriately.

Analog PLL

The Fractional-N (Frac-N) Analog PLL supports high-frequency clock generation from one of three clock sources (See Register 201: PLL CONFIG5).

It can be configured without the need for any additional system clock. Write-only access to the PLL configuration registers is available via a

synchronous I2C interface.

The PLL registers may be written using the I2C Synchronous Slave Interface. No system clock is required. These registers are write-only.

The PLL registers may be read back using the I2C Slave Interface. A system clock is required for readback. These PLL registers are read-

only by default. If a system clock is already present, write access for the PLL registers may be enabled with mcu_configure_pll.

External Jack Detection Integration

This is a new feature of the ES9219. Feature description to be added in next revision.

ES9219 датащи(PDF) 19 Page - ESS Technology,Inc