AM79C850 datasheet(13/97 Pages) AMD

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P R E L I M I N A R Y

AMD

SUPERNET 3

Data Strobe/ (TTL input, active low)

– Asynchronous when NPMODE = 0

– Synchronous when NPMODE = 1

The

DS input (active low) is used in the handshake

between the NP and SUPERNET 3 when the

SUPERNET 3 acts as bus slave during register

accesses. In the asynchronous mode, this input signal is

set by the node processor to transfer data between the

NP and the SUPERNET 3. The direction of the data

transfer is dictated by the logic level of the R/

W line. The

NP sets

DS low to initiate a data transfer. DS is not used

in the synchronous mode. The chip-select input (

CSI)

must be low while

DS is low in order to start an NP

bus transaction.

NPADDR7–0

NP Address Bus (TTL input)

The NPADDR7–0 input lines allow direct access to

SUPERNET 3 internal registers. In addition, these

lines are used to place SUPERNET 3 into different

operating states.

The NPADDR bus of the SUPERNET 3 performs two

control functions. First, the input on NPADDR7–0 acts

as an address, selecting the proper internal register for a

read or write operation that is controlled by the R/

W pin.

The data is either read onto or loaded from the 16-bit

NP bus. For a discussion of the results of read and load

instructions, see the section under Programming

the FORMAC Plus in the SUPERNET 2 data book.

Second, instructions or commands can be issued to

SUPERNET 3 by using the NPADDR bus.

NPDATA15–0

NP Data Bus (TTL input, TTL output, high

impedance)

The NP data bus is a 16-bit wide bidirectional data bus

used to interface the SUPERNET 3 to the node

processor. Data transfer on the NP data bus can be

synchronous or asynchronous depending upon the

setting of the NPMODE pin. For asynchronous opera-

tion, a two-wire handshake is provided through the

READY and data-strobe (DS) lines.

NPMODE

NP Bus Mode (TTL input)

The level on the NPMODE pin defines the type of

NP-bus interface with the SUPERNET 3. When

NPMODE is strapped high, the NP interface operates

synchronously with BCLK. When NPMODE is strapped

low, asynchronous interface operation is selected.

READY

Ready (TTL output, open drain, active low, high

impedance)

In asynchronous mode, the

READY output (active low)

is used in the handshake between the NP and

SUPERNET 3. The SUPERNET 3

READY output

provides an asynchronous acknowledgment to the NP

that data transfer is complete. The SUPERNET 3

asserts

READY when it has put the data onto the NP bus

during a read cycle, or when it has taken the data from

the NP bus during a write cycle.

READY is a response to

the

CSI and DS inputs, and returns high after the CSI or

DS signals go high.

In the synchronous mode, the

READY line goes active

on the BCLK edge when

CSI and DS are active. READY

goes inactive on the following BCLK edge. In the case of

loading/reading of the MDR (memory data register),

READY goes active on the BCLK edge after the

completion of any pending data transfer from/to

buffer memory.

R/W

Read/Write Select (TTL input)

The R/

W line is used to select the type of access (i.e.,

read or write) between the SUPERNET 3 and the NP. If

W is high, data is read from the SUPERNET 3 to the

NP. If R/

W is low, the data flow is from the NP to the

SUPERNET 3.

MINTR1

Maskable Interrupt 1 (TTL output, open drain, high

impedance)

The

MINTR1 output (active low) is an attention line to

the NP.

MINTR1, when active, indicates an interrupt due

to one or more unmasked flags in status register 1. In

general, the active state of

MINTR1 indicates that an

unmasked interrupt condition or a transmit condition has

occurred.

MINTR1 is deactivated once either the lower

or upper 16 bits of status register 1 (ST1L or ST1U) are

read. Once

MINTR1 is asserted, all 32 bits of status

this pin.

MINTR2

Maskable Interrupt 2 (TTL output, open drain, high

impedance)

The

MINTR2 output (active low) is an attention line to

the NP.

MINTR2, when active, indicates an interrupt due

to one or more unmasked flags in status register 2. In

general, the active state of

MINTR2 indicates that an

unmasked interrupt condition, a receive condition, or a

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