AM79C850 datasheet(35/97 Pages) AMD

35 / 97 page

P R E L I M I N A R Y

AMD

SUPERNET 3

Addition of Scrambler/Descrambler Function to

Support Copper PMD

This is a description of the Stream-Cipher Scrambler

and Descrambler as implemented in the physical layer

controller block.

The Stream-Cipher Scrambler adds the output of a

random generator to the data stream. The purpose is to

spread the spectrum and reduce frequency peaks. As a

result, higher signal amplitudes can be transmitted over

copper that meet the requirements of the FCC and other

regulatory agencies.

The random generator is the polynomial 211 + 29. The

SUPERNET 3 implementation uses a 5-bit parallel

technique. The 5-bit output of the random generator is

exclusive-ORed with the input to produce scrambled

data for transmission.

The descrambler has a random generator which is

identical to the random generator in the scrambler. The

output of this generator is used to decipher the received

scrambled data using the same exclusive-OR function.

Since both random generators are identical, the output

of the receiver random generator is the original data

(data XOR Random

→ XOR Random = data).

This process is open loop in nature, i.e., the data has no

effect on the states of the random generators. There-

fore, the descrambler must incorporate synchronization

circuitry to preset its state to the same state as the

scrambler. Once both random generators start from the

same state, they will remain in synchronization.

The synchronization circuitry, CREG and HREG regis-

ters, are designed to take advantage of the scrambled

FDDI line states. During the line states (HLS, QLS, MLS

and ILS), CREG and HREG generate known patterns.

When the synchronization circuitry detects these pat-

terns, it generates a capture signal and the correspond-

ing output data pattern.

CAPTURE controls the random generator. When it is

false, the random generator operates open loop. When

it is true, the random generator is preset to the deduced

output data exclusive-ORed with the input scrambled

data. This is equal to the state of the scrambler’s

random generator.

FDDI Line States & Detected Signals

Line State

Data Bits

Detected Bits

HLS

00010000100

00111001110

QLS

00000000000

MLS

00000000100

00000001110

ILS

11111111111

CAPTURE is enabled by SAMPLE, which is enabled by

SCRM_RESYNC. SCRM_RESYNC is active when

PHY line state is not Active Line State, or Unknown Line

State. A false SCRM_RESYNC indicates that the

decoded data is correct. Therefore the random genera-

tor is synchronized and SAMPLE is set false. SAMPLE

is set true when SCRM_RESYNC is true except during

the following condition:

If two consecutive IDLE bytes and then non-idle bytes

are detected when SCRM_RESYNC is true, SAMPLE

goes false and stays false for 32 RSCLK cycles. After

that

the

state

SAMPLE

depends

SCRM_RESYNC.

Testability

The Test Access Port (TAP)

An IEEE 1149.1 boundary-scan architecture is provided

for board level testing and diagnostics. All pins are part

of the boundary-scan ring except Digital Transmitter/

Receiver pseudo-analog (PECL) pins. The TAP con-

sists of five pins, TCK, TMS, TDI, TDO and

TRST.

These pins are dedicated connections and may not be

used for any other purpose. The boundary-scan

architecture includes a TAP controller, an instruction

The functional description of the TAP that follows is not a

complete description of the IEEE boundary-scan

architecture. Additional information and a more detailed

functional description can be found in the standard

document (IEEE Std 1149.1–1990). The description

provided

here

covers

the

specifics

this

particular implementation.

TAP Controller

The TAP controller is a synchronous 16-state finite state

machine which is driven by the TCK and TMS pins. All

state transitions of the TAP controller occur at the rising

edge of TCK. The transitions are based on the value of

TMS at the rising edge of TCK. In the Test-Logic-Reset

state the instruction register is initialized with the

IDCODE instruction. The TAP controller is forced to the

Test-Logic-Reset state whenever a logic 0 is placed on

the

TRST pin. A system reset has no effect on the

TAP controller.

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