AM79C850 datasheet(49/97 Pages) AMD

49 / 97 page

P R E L I M I N A R Y

AMD

SUPERNET 3

In either method, the

DS is ignored and should be

inactive (HIGH) during all synchronous accesses. The

read cycle is initiated by asserting the

CSI, NPADDR,

NPRW signal which is sampled by the rising edge of the

clock. The NPRW signal should be high for read and low

for write. At least one clock cycle after the sampling

edge, the SUPERNET 3 will begin to drive the NP bus,

and this allow the chip driving the NP bus in the previous

read or write cycle time to tristate the NP bus. After the

next rising edge of clock (the second rising edge after

the assertion of

CSI) the data on the NP bus will be valid

and the

READY signal will be asserted. The data will

remain valid until the second rising edge of clock after

the de-assertion of

CSI. The SUPERNET 3 will tristate

the NP bus within 1/2 clock cycle after this clock edge.

Regardless of how many clock cycles are needed for

executing any SUPERNET 3 instruction,

READY stays

active only for one clock cycle.

A write cycle is very similar to the read cycle. The

principal difference are as follows:

1. The NPRW signal must be low while

CSI is asserted.

2. The data written must be valid on the second rising

edge of clock after

CSI is asserted and remain valid

until the next rising edge of the clock and

READY

signal goes active (i.e. LOW). Regardless of how

many clock cycles are needed for executing any

SUPERNET 3 instruction,

READY stays active only

for one clock cycle.

The Node Processor must tristate the NP bus within one

half clock period after the second rising edge after the

assertion of

CSI. The Node Processor can extend the

write cycle and the time it has to tristate the NP bus by

delaying the de-assertion of

CSI signal.

All register access is complete in two cycles and

READY

is asserted at the positive edge of the second clock

cycle. An exception is for MDR accesses that may take

more than two clock cycles, at which point the assertion

READY is deferred until the last clock period of the

execution cycle. Regardless of how many clock cycles

are needed for executing any SUPERNET 3 instruction,

READY stays active only for one clock cycle. Refer to

timing diagrams in specifications for details. The

assertion of

READY signal could be delayed during

MDR accesses by “n” multiples of clock period.

Address Filter (AF) Support

XDA_XACT and XSA_XACT input signals are provided

for the external CAM.

XDA_XACT

External Destination Address Exact Match (input,

active low)

This input indicates whether the external address match

was exact (low) or inexact (high). This input should

remain asserted for at least one BCLK cycle, and must

be deasserted for at least one BCLK cycle before a

subsequent external source address match is recog-

nized. It must be asserted and deasserted in an identical

fashion to the

XDAMAT pin. This input is used in

conjunction with the

XDAMAT pin as follows:

Match

Action

XDA_XACT and XDAMAT

A, C indicators set

and frame copied*.

XDA_XACT and XDAMAT

Invalid combination.

Ignored by MAC.

XDA_XACT and

XDAMAT

A, C indicators not set

and frame copied.

XDA_XACT and XDAMAT

No action.

*Frame is copied if valid frame or if in promiscuous or limited

promiscuous mode. In OSM, the A, C indicators are set ac-

cording to the OSM rules if both bit 4 and bit 5 (MEIND0,1) of

MDREG3 are not set.

The

XDA_XACT pin, which is generated by the external

AF, is logically ORed with the “af_dax” output signal

generated by the internal AF logic. This pin is enabled

only if the MENXACT bit in the mode register 3

(MDREG3) is set. This pin should be tied high (VCC)

when external address detection (an external AF) is

not used.

XSA_XACT

External Source Address Exact Match (input,

active low)

This input indicates whether the external source ad-

dress match was exact (low) or inexact (high). This input

should remain asserted for at least one BCLK cycle, and

must be deasserted for at least one BCLK cycle before a

subsequent external source address match is recog-

nized. It must be asserted and deasserted in an identical

fashion to the

XSAMAT pin. This input is used in

conjunction with the

XSAMAT pin as follows:

Match

Action

XSA_XACT and XSAMAT

Frame stripped.

XSA_XACT and XSAMAT

Invalid combination.

Ignored by MAC.

XSA_XACT and

XSAMAT

Frame not stripped.

XSA_XACT and XSAMAT

No action.

The

XSA_XACT pin which is generated by the external

AF is logically ORed with the “af_sax” output signal

generated by the internal AF logic. This pin is enabled

only if the MENXACT bit in the mode register 3

(MDREG3) is set. This pin should be tied high (VCC)

when external address detection (an external AF) is

not used.

Introduction

The Address Filter (AF) is a functional block that

extends the group and/or individual MAC address

recognition capabilities of the core FDDI MAC. The AF

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