56F8335 datasheet(19/160 Pages) FREESCALE

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Signal Pins

56F8335 Technical Data, Rev. 1

Freescale Semiconductor

Preliminary

CLKO

Output

Tri-Stated

Clock Output — This pin outputs a buffered clock signal. Using

the SIM CLKO Select Register (SIM_CLKOSR), this pin can be

programmed as any of the following: disabled, CLK_MSTR

(system clock), IPBus clock, oscillator output, prescaler clock

and postscaler clock. Other signals are also available for test

purposes.

See Part 6.5.7 for details.

(GPIOA0)

Output

Schmitt

Input/

Output

Tri-stated

Input

Address Bus — A8 - A13 specify six of the address lines for

external program or data memory accesses. Depending upon

the state of the DRV bit in the EMI bus control register (BCR), A8

- A13 and EMI control signals are tri-stated when the external

bus is inactive.

Port A GPIO — These six GPIO pins can be individually

programmed as input or output pins.

After reset, these pins default to address bus functionality and

must be programmed as GPIO.

To deactivate the internal pull-up resistor, clear the appropriate

GPIO bit in the GPIOA_PUR register.

Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.

Note: Primary function is not available in this package

configuration; GPIO function must be used instead.

(GPIOA1)

A10

(GPIOA2)

A11

(GPIOA3)

A12

(GPIOA4)

A13

(GPIOA5)

GPIOB0

(A16)

Schmitt

Input/

Output

Input

Tri-stated

Port B GPIO — These four GPIO pins can be individually

programmed as an input or output pin.

Address Bus — A16 - A19 specify four of the address lines for

external program or data memory accesses. Depending upon

the state of the DRV bit in the EMI bus control register (BCR),

A16 - A19 and EMI control signals are tri-stated when the

external bus is inactive.

After reset, the default state is GPIO.

To deactivate the internal pull-up resistor, clear bit 0 in the

GPIOB_PUR register.

Example: GPIOB1, clear bit 1 in the GPIOB_PUR register.

GPIOB1

(A17)

GPIOB2

(A18)

GPIOB3

(A19)

Table 2-2 Signal and Package Information for the 128-Pin LQFP

Signal

Name

Pin No.

Type

State

During

Reset

Signal Description

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