56F8335 datasheet(61/160 Pages) FREESCALE

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Peripheral Memory Mapped Registers

56F8335 Technical Data, Rev. 1

Freescale Semiconductor

Preliminary

Table 4-32 GPIOD Registers Address Map

(GPIOD_BASE = $00 F320)

Address Offset

Reset Value

GPIOD_PUR

Pull-up Enable Register

0 x 1FFF

GPIOD_DR

Data Register

0 x 0000

GPIOD_DDR

Data Direction Register

0 x 0000

GPIOD_PER

Peripheral Enable Register

0 x 1FC0

GPIOD_IAR

Interrupt Assert Register

0 x 0000

GPIOD_IENR

Interrupt Enable Register

0 x 0000

GPIOD_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOD_IPR

Interrupt Pending Register

0 x 0000

GPIOD_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOD_PPMODE

Push-Pull Mode Register

0 x 1FFF

GPIOD_RAWDATA

Raw Data Input Register

—

Table 4-33 GPIOE Registers Address Map

(GPIOE_BASE = $00 F330)

Address Offset

Reset Value

GPIOE_PUR

Pull-up Enable Register

0 x 3FFF

GPIOE_DR

Data Register

0 x 0000

GPIOE_DDR

Data Direction Register

0 x 0000

GPIOE_PER

Peripheral Enable Register

0 x 3FFF

GPIOE_IAR

Interrupt Assert Register

0 x 0000

GPIOE_IENR

Interrupt Enable Register

0 x 0000

GPIOE_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOE_IPR

Interrupt Pending Register

0 x 0000

GPIOE_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOE_PPMODE

Push-Pull Mode Register

0 x 3FFF

GPIOE_RAWDATA

Raw Data Input Register

—

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