56F8335 datasheet(34/160 Pages) FREESCALE

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56F8335 Technical Data, Rev. 1

Freescale Semiconductor

Preliminary

Figure 3-4 Connecting an External Clock Signal Register

3.3 Registers

When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the

NOT contain this oscillator.

Part 4 Memory Map

4.1 Introduction

The 56F8335 and 56F8135 devices are 16-bit motor-control chips based on the 56800E core. These parts

use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip

RAM and Flash memories are used in both spaces.

This section provides memory maps for:

•

Program Address Space, including the Interrupt Vector Table

•

Data Address Space, including the EOnCE Memory and Peripheral Memory Maps

On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions are

identified in the “Use Restrictions” column of Table 4-1.

Note: Data Flash and Program RAM are NOT available on the 56F8135 device.

Table 4-1 Chip Memory Configurations

On-Chip Memory

56F8335

56F8135

Use Restrictions

Program Flash

64KB

Erase / Program via Flash interface unit and word writes to

CDBW

Data Flash

8KB

—

Erase / Program via Flash interface unit and word writes to

CDBW. Data Flash can be read via either CDBR or XDB2,

but not by both simultaneously

Program RAM

4KB

—

None

Data RAM

8KB

None

Program Boot Flash

8KB

Erase / Program via Flash Interface unit and word writes to

CDBW

XTAL

EXTAL

External

VSS

Clock

Note: When using an external clocking

source with this configuration, the input

“CLKMODE” should be high and COHL bit in

the OSCTL register should be set to 1.

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