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SH7041A датащи(PDF) 272 Page - Renesas Technology Corp

номер детали SH7041A
подробное описание детали  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A датащи(HTML) 272 Page - Renesas Technology Corp

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Figure 11.4 shows the changes in priority levels when transfer requests are issued simultaneously
for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The
DMAC operates in the following manner under these circumstances:
1. Transfer requests are issued simultaneously for channels 0 and 3.
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is conducted
first (channel 3 is on transfer standby).
3. A transfer request is issued for channel 1 during a transfer on channel 0 (channels 1 and 3 are
on transfer standby).
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer
comes first (channel 3 is on transfer standby).
6. When the channel 1 transfer ends, channel 1 shifts to the lowest priority level.
7. Channel 3 transfer begins.
8. When the channel 3 transfer ends, channel 3 and channel 2 priority levels are lowered, giving
channel 3 the lowest priority.
Transfer request
Channel waiting
DMAC operation
Channel priority
Issued for
channels 0 and 3
Issued for channel 1
0
> 1 > 2 > 3
Channel 0
transfer begins
1
> 2 > 3 > 0
Channel 0
transfer ends
Channel 1
transfer begins
Channel 3
transfer begins
2
> 3 > 0 > 1
Channel 1
transfer ends
0
> 1 > 2 > 3
Channel 3
transfer ends
Change of
priority
Change of
priority
Change of
priority
None
3
3
1,3
Figure 11.4 Example of Changes in Priority in Round Robin Mode



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