SH7041A datasheet(269/923 Pages) RENESAS

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transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon

the input of a transfer request signal.

The transfer request source need not be the data transfer source or transfer destination. However,

when the transfer request is set by RxI (transfer request because SCI’s receive data is full), the

transfer source must be the SCI’s receive data register (RDR). When the transfer request is set by

TxI (transfer request because SCI’s transmit data is empty), the transfer destination must be the

SCI’s transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the

data transfer destination must be the A/D converter register.

Table 11.4

Selecting On-Chip Peripheral Module Request Modes with the RS Bits

RS3 RS2 RS1 RS0

DMAC Transfer

Request Source

DMA Transfer

Request Signal Source

Destin-

ation

Bus Mode

0110

MTU*

TGI0A

Any*

Burst/cycle steal

0111

MTU*

TGI1A

Any*

Burst/cycle steal

1000

MTU*

TGI2A

Any*

Burst/cycle steal

1001

MTU*

TGI3A

Any*

Burst/cycle steal

1010

MTU*

TGI4A

Any*

Burst/cycle steal

1011

A/D

ADI*

ADDR*

4 Any*1

Burst/cycle steal

1100

SCI0*

3 transmit blockTxI0

Any*

TDR0

Burst/cycle steal

1101

SCI0*

3 transmit blockRxI0

RDR0

Any*

Burst/cycle steal

1110

SCI1*

3 transmit blockTxI1

Any*

TDR1

Burst/cycle steal

1111

SCI1*

3 transmit blockRxI1

RDR1

Any*

Burst/cycle steal

Notes: *1 External memory, memory-mapped external device, on-chip memory, on-chip

peripheral module (excluding DMAC, DTC, BSC, UBC).

*2 MTU: Multifunction timer pulse unit.

*3 SCI0, SCI1: Serial communications interface.

*4 ADDR0, ADDR1: A/D converter’s A/D register.

*5 ADI1 for A mask.

In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt

enable bit for each module, and output an interrupt signal.

When an on-chip peripheral module’s interrupt request signal is used as a DMA transfer request

signal, interrupts for the CPU are not generated.

When a DMA transfer is conducted corresponding with one of the transfer request signals in table

11.4, it is automatically discontinued. In cycle steal mode this occurs in the first transfer, and in

burst mode with the last transfer.

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