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DS00002774G-page 17

USB4712

5.1

Boot Sequence

5.1.1

STANDBY MODE

If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-

mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream

ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no

states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order

to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode

and must be re-initialized after RESET_N is negated high.

5.1.2

SPI INITIALIZATION STAGE (SPI_INIT)

The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,

the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal

firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid

signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the SPI

Firmware/external SPI ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If

a valid signature is not found, then execution continues from internal ROM (CFG_ROM stage).

When using an external SPI ROM, a minimum of 2.2 Mbit is required, and 60 MHz or faster SPI ROM must be used.

Both 1- and 2-bit SPI ROM are supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0

and mode 3 SPI flashes are supported.

If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_ROM stage).

5.1.3

CONFIGURATION FROM INTERNAL ROM STAGE (CFG_ROM)

In this stage, the internal firmware loads the default values from the internal ROM. Most of the hub configuration regis-

ters, USB descriptors, electrical settings, etc. will be initialized in this state even when running from SPI.

5.1.4

OTP CONFIGURATION STAGE (CFG_OTP)

Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The

default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-

grammed.

5.1.5

HUB CONNECT STAGE (USB_ATTACH)

Once the hub registers are updated through default values, SMBus master, and OTP, the device firmware will enable

attaching the USB host by setting the USB_ATTACH bit in the HUB_CMD_STAT register. The device will remain in the

Hub Connect stage indefinitely until the VBUS function is deasserted/assertion of external RESET_N pin.

5.1.6

NORMAL MODE (NORMAL_MODE)

Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB

Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the USB

Host.

If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated

hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub Connect stage until

the soft disconnect is negated.