USB4712 datasheet(11/43 Pages) MICROCHIP

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 2018-2021 Microchip Technology Inc.

DS00002774G-page 11

USB4712

SMBus 1 Data

SMB1_DAT

I/OD12

SMBus 1 Master Data

Note:

Not available on USB4712PF - HFC is dis-

abled by default.

SMBus 2 Clock

SMB2_CLK

I/OD12

SMBus 2 SLAVE

Note:

Disabled on USB4712PF to prevent interfer-

ence with FlexConnect operation.

SMBus 2 Data

SMB2_DAT

I/OD12

SMBus 2 SLAVE

Note:

Disabled on USB4712PF to prevent interfer-

ence with FlexConnect operation.

UART Interface Pins

UART Transmit

UART_TX

O12

UART Transmit

Note:

Not available on USB4712PF - HFC is dis-

abled by default.

UART Receive

UART_RX

UART Receive

Note:

Not available on USB4712PF - HFC is dis-

abled by default.

Miscellaneous

General

Purpose

Input/Output

6, 11

GPIO6

GPIO11

I/O12

General purpose inputs/outputs 6, 11.

Note:

GPIOs not available on USB4712PF - HFC is

disabled by default.

VBUS

Detection

VBUS_DET

This signal detects the state of the upstream bus power.

When designing a detachable hub, this pin must be con-

nected to the VBUS power pin of the upstream USB port

through a resistor divider (50 kΩ by 100 kΩ) to provide

3.3 V.

For self-powered applications with a permanently

attached host, this pin must be connected to either 3.3 V

or 5.0 V through a resistor divider to provide 3.3 V. In

embedded applications, VBUS_DET may be controlled

(toggled) when the host desires to renegotiate a connec-

tion without requiring a full reset of the device.

Reset Input

RESET_N

This active low signal is used by the system to reset the

device. The active low pulse should be at least 1

s wide.

Bias Resistor

RBIAS

I-R

A 12.0 k

 1.0% resistor is attached from ground to this

pin to set the transceiver’s internal bias settings. Place

the resistor as close to the device as possible with a dedi-

cated, low impedance connection to the GND plane.

External 25 MHz

Crystal Input

XTALI

ICLK

External 25 MHz crystal input.

External 25 MHz

Reference Clock

Input

CLK_IN

ICLK

External reference clock input.

The device may alternatively be driven by a single-ended

clock oscillator. When this method is used, XTALO

should be left unconnected.

External 25 MHz

Crystal Output

XTALO

OCLK

External 25 MHz crystal output.

TABLE 3-2:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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