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DS00002774G-page 29

USB4712

9.6

AC Specifications

This section details the various AC timing specifications of the device.

9.6.1

POWER SUPPLY AND RESET_N SEQUENCE TIMING

Figure 9-2 illustrates the recommended power supply sequencing and timing for the device. RESET_N and/or VBUS_-

DET should rise after or at the same rate as VDDIO33/VDDPLLREF33. VBUS_DET and RESET_N do not have any

other timing dependencies.

9.6.2

POWER-ON AND CONFIGURATION STRAP TIMING

Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where

RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following

9.2, "Operating Conditions**," on page 26.

Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, "Reset and Con-

figuration Strap Timing" for additional details.

FIGURE 9-2:

POWER SUPPLY AND RESET_N SEQUENCE TIMING

TABLE 9-4:

POWER SUPPLY AND RESET_N SEQUENCE TIMING

Symbol

Description

Min

Typ

Max

Units

VDDIO33/VDDPLLREF33 to RESET_N/VBUS_DET rise time

0

ms

FIGURE 9-3:

POWER-ON CONFIGURATION STRAP VALID TIMING

TABLE 9-5:

POWER-ON CONFIGURATION STRAP LATCHING TIMING

Symbol

Description

Min

Typ

Max

Units

Configuration strap hold after external power supplies at opera-

tional levels

1

ms

VDDIO33/

VDDPLLREF33

RESET_N/

VBUS_DET

All External

Power Supplies

Configuration

Straps