Signals description

NAND01G-N

14/23

Rev1.0

2.12

LPSDRAM Address Inputs (A0-A12)

The A0-A12 Address Inputs are used by the LPSDRAM to select the row or column to be

made active. If a row is selected, all thirteen, A0-A12 Address Inputs are used. If a column is

selected, only the nine least significant Address Inputs, A0-A8, are used. In this latter case,

A10 determines whether Auto Precharge is used. If A10 is High (set to ‘1’) during Read or

Write, the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to

‘0’) during Read or Write, the Read or Write cycle does not include an Auto Precharge cycle.

2.13

LPSDRAM Bank Select Address Inputs (BA0-BA1)

The BA0 and BA1 Banks Select Address Inputs are used by the LPSDRAM to select the

bank to be made active.

2.14

LPSDRAM Data Inputs/Outputs (DQ0-DQ15)

On the LPSDRAM, DQ0-DQ15 output the data stored at the selected address during a

Read operation, or are used to input the data during a write operation.

2.15

The Chip Select input E activates the LPSDRAM state machine, address buffers and

2.16

LPSDRAM Column Address Strobe (CAS)

The Column Address Strobe, CAS, is used in conjunction with Address Inputs A8-A0 and

BA1-BA0, to select the starting column location prior to a Read or Write.

2.17

LPSDRAM Row Address Strobe (RAS)

The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and

BA1-BA0, to select the starting address location prior to a Read or Write.

2.18

The LPSDRAM Write Enable input, W, controls writing to the LPSDRAM.