NAND01G-N

Signals description

Rev1.0

13/23

2.6

Flash memory Read Enable (R)

The NAND Flash memory Read Enable pin, R, controls the sequential data output during

Read operations. The falling edge of R also increments the internal column address counter

by one.

2.7

The NAND Flash memory Write Enable input, W, controls writing to the Command Interface,

Input Address and Data latches. Both addresses and data are latched on the rising edge of

Write Enable.

2.8

Flash memory Write Protect (WP)

The Write Protect pin is a NAND Flash memory input that gives a hardware protection

Flash memory device does not accept any program or erase operations.

2.9

Flash memory Ready/Busy (RB)

The Ready/Busy output, RB, is an open-drain NAND Flash memory output that can be used

to identify if the P/E/R Controller is currently active.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.10

the main power supply for all operations (read, program and erase).

2.11

connected to the system ground.