TUSB6250 datasheet(32/124 Pages) TI

32 / 124 page

Microcontroller Unit (MCU)

6−9

SLLS535A − January 2004

TUSB6250

Table 6−3. SFR Map [IDATA: 80 FF] (Shaded Area Indicates ESFRs) (Continued)

DESCRIPTION

LABEL

ADDRESS

→ DF is used for scratch pad (see Note 3)

→ DF

Accumulator

Interrupt enable register 1

IE1

B register

RTK timer register

RTKTM

Vector interrupt register

VECINT

Interrupt priority register 1

IP1

PC copy register (LB)

PCL

PC copy register (HB)

PCH

Watchdog timer CSR

WDCSR

MCU configuration register

MCUCNFG

Power-on reset and suspend detection register

PWONSUSP

Reserved

NOTES:

1. ESFRs (BE−CF) are write protected when LJMP to the application is executed. When LJMP to the monitor is executed or when MCU

writes 55h to the BPSTA register these registers become unprotected.

2. Application firmware should not write to the space marked as RESERVED.

3. These locations are reserved as the monitor working area and applications should not use them.

6.3.1 PCON: Power Control Register (at SFR 87h)

The PCON is the standard 8051 power control register. The PCON register is cleared by a power-up reset

or a watchdog timer (WDT) reset. The PCON register also be cleared by a USB reset, when the function reset

connection bit in the USBCTL register is set (FRSTE = 1).

765

43210

SMOD

RSV

GF1

FG0

RSV

IDL

R/W

R/O

R/W

R/O

R/W

BIT

NAME

RESET

FUNCTION

IDL

MCU idle mode bit. This bit can be set by the MCU and is cleared by the assertion of any enabled

interrupt. It is not recommended to use the MCU idle mode during normal operation of the TUSB6250

controller.

RSV

Reserved = 0

3−2

GF [1:0]

General-purpose bits. The MCU can write and read these bits.

6−4

RSV

Reserved = 0

SMOD

Double baud rate control bit. For more information see the UART serial interface in the M8051 core

specification.

6.3.2 RTKTM: RTK Timer Register (at ESFR F6h)

The RTK timer counter is a down counter with its initial value loaded from the RTK timer value specified in the

RTKTM register. A 10-

µs clock is used for the RTK timer counter. When the value in the down counter reaches

zero, an interrupt pulse is generated (connected to INT6) and the RTKTM value is reloaded into the counter.

This register provides an interrupt period of 10

µs to 2550 µs. Any write to this counter clears the original

content of the counter and causes the counter to restart the down count from the new timer value.

The RTKTM register is cleared by a power-up reset or a WDT reset. The RTKTM register can also be cleared

by a USB reset, when the function reset connection bit in the USBCTL register is set (FRSTE = 1).

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