DS2792 Programmable Fuel Gauge with UART Interface

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Note that both the FE and the serial mode bit 0 (SM0) share the same bit location in the SCON register, but this

information is actually stored in different registers. The setting of FEDE in the SMD register determines which

register is accessed: logic 0 allows access to the SM0 bit and a logic 1 allows access to the FE bit. The FEDE must

be set to 1 while reading or writing the FE bit.

Multiprocessor Communication Mode

Multiprocessor communication mode makes special use of the 9th data bit in modes 2 and 3 if the SM2 bit of the

SCON register is set. If enabled, the 9th data bit is used to signify that the incoming byte is an address. This allows

the processor to be interrupted only if the correct address is received as defined by the serial address (SADDR)

and serial address enable (SADEN) registers. The receive interrupt, if enabled, will only occur when a recognized

address is received.

When multiprocessor mode is enabled and a serial word is received with the 9th bit set, the byte will be assumed to

be an address. The address will be compared to an internally stored address. If it matches, a receive interrupt will

occur. The internal address is derived from the SADDR and SADEN registers. The SADDR register specifies an

absolute address. This is the user specified address of the device. The SADEN register indicates which address

bit(s) will be used in the comparison. This allows broadcast transmissions that reach multiple microcontrollers or all

microcontrollers on the serial interface. The user defines this protocol.

Software will write an 8-bit address to the SADDR register. This is the microcontroller’s individual address. Any bit

in SADEN that contains logic 0 will cause the corresponding bit in SADDR to be ignored in comparison. Thus, logic

0 bits in SADEN create don’t care bit states for address comparisons. When an address is received, each address

bit that is not masked by a don’t care will be compared to the SADDR. The microcontroller will interrupt on any

address that matches this comparison. Any address that meets this comparison is called a given address. The

following example shows how one address can be directed to an individual processor or two out of three.

Micro 1

Micro 2

Micro 3

SADDR 11110000

SADDR 11110001

SADDR 11110010

SADEN 11111010

SADEN 11111001

SADEN 11111010

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Given

11110x0x

Given

11110xx1

Given

11110x1x

Note that an address of 11110000 reaches only microcontroller 1. An address of 11110001 reaches microcontroller

1 and microcontroller 2. An address of 11110010 reaches only microcontroller 3. The microcontroller also matches

on any address that corresponds to the broadcast address. This is the logical OR of the SADDR and SADEN

registers, with any 0s defined as don’t cares.

UART Interrupts

Interrupts generated by the serial interface are controlled through the serial interface interrupt register (SINT) and

the serial interface interrupt mask register (SMASK). Writing either the receive interrupt mask (MRI) bit or transmit

interrupt mask (MTI) bit to 1 will enable interrupts to occur whenever the corresponding transaction successfully

completes. Writing either of these bits to 0 disables the corresponding interrupt. The RINT, TINT bits of the SMASK

are a logical AND of the RI flag, TI flag bits of the control register, and the corresponding interrupt mask bits.

Upon successful reception of a data word on RXD, the RI flag of the SCON register will be set. If MRI is set to 1,

the RINT flag will be set and an interrupt will be generated. System software can then read the SINT register to

determine the source of the interrupt. The RINT flag and the interrupt are cleared by writing the RI flag to 0. After

transmission of a data word on TXD, the TI flag of the SCON register will be set. If MTI is set to 1, the TINT flag will

be set and an interrupt will be generated. System software can then read the SINT register to determine the source

of the interrupt. The TINT flag and the interrupt are cleared by writing the TI flag to 0.