DS2792 Programmable Fuel Gauge with UART Interface

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SUSPEND TIMER

The suspend timer allows the DS2792 to periodically monitor the cell while spending the majority of its time in a

low-power state. Suspend operation is managed through the coulomb counter control register (CCCON). A timout

value between 0.5s and 2.0s can be selected through the suspend timeout bits (CCSUS). When the suspend timer

is enabled and a timeout occurs, the DS2792 will transition from SLEEP mode to ANALOG mode, and eventually to

CPU mode. Upon transition to ANALOG mode, the coulomb counter enable bit (CCEN) is automatically set and the

ADC block becomes active. The DS2792 may then perform all needed cell-monitoring operations before clearing

the CCEN bit and returned to SLEEP mode. The process repeats after each timeout.

Figure 6. CCCON Register Format

FIELD

BIT

FORMAT

ALLOWABLE VALUES

Reserved

7:3

Read Only

Undefined

CCSUS

2:1

R/W

Suspend Timeout

0 0 = Suspend Timeout Disabled

0 1 = 0.5s timeout

1 0 = 1.0s timeout

1 1 = 2.0s timeout

CCEN

0

R/W

Coulomb Counter Enable

0 = ADC block disabled

1 = ADC block enabled

REGISTER SET

Most functions of the device are controlled by sets of registers. These registers provide a working space for

memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided

into two major types: system registers and peripheral registers. The common register set, also known as the

system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack

pointer. The peripheral registers define additional functionality that may be included by different products based on

the MAXQ20 architecture. This functionality is broken up into discrete modules so that only the features required

for a given product need to be included. Tables 1 through 6 detail the DS2792 register set.

Table 1. System Register Map

MODULE NAME (BASE SPECIFIER)

REGISTER

INDEX

AP (8h)

A (9h)

PFX (Bh)

IP (Ch)

SP (Dh)

DPC (Eh)

DP (Fh)

00h

AP

A[0]

PFX

IP

—

—

—

01h

APC

A[1]

—

—

SP

—

—

02h

—

A[2]

—

—

IV

—

—

03h

—

A[3]

—

—

—

Offs

DP0

04h

PSF

A[4]

—

—

—

DPC

—

05h

IC

A[5]

—

—

—

GR

—

06h

IMR

A[6]

—

—

LC0

GRL

—

07h

—

A[7]

—

—

LC1

BP

DP1

08h

SC

A[8]

—

—

—

GRS

—

09h

—

A[9]

—

—

—

GRH

—

0Ah

—

A[10]

—

—

—

GRXL

—

0Bh

IIR

A[11]

—

—

—

FP

—

0Ch

—

A[12]

—

—

—

—

—

0Dh

—

A[13]

—

—

—

—

—

0Eh

CKCN

A[14]

—

—

—

—

—

0Fh

WDCN

A[15]

—

—

—

—

—

Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits

wide. Registers in module AP are bit addressable.