DS2792 Programmable Fuel Gauge with UART Interface

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SERIAL INTERFACE MODULE

The DS2792 supports a universal asynchronous receiver/transmitter (UART) module for serial communication with

framing error detection and automatic address recognition. The UART is initialized through a configuration register

(SMD). Communication is managed through a control register (SCON) and a transmit/receive register (SBUF). The

SBUF register location provides access to both transmit and receive registers, where a read is directed to the

receive buffer and a write is directed to the transmit buffer. SBUF allows the serial interface to receive an incoming

word before software has read the previous one provided SBUF is read before the stop bit of the next word is

recieved.

If the DS2792 detects a start bit of an incoming transmission while in SLEEP mode, the instruction clock will be

enabled to allow reception of data. Note that the instruction clock will not achieve accuracy tolerance required for

UART communication unless the analog oscillator is also active. All outgoing transmission must be completed, and

the RXD pin must be in the inactive logic state (see RXDi bit), before the DS2792 will transition back to SLEEP

mode.

Figure 10. Serial Interface Control Register (SCON)

FIELD

BIT

FORMAT

ALLOWABLE VALUES

FE/SM0

7

R/W

Serial Interface Mode Bit 0/Framing Error Flag

The operation of this bit depends on the state of the FEDE bit

of the SMD register. When FEDE is cleared to 0, this bit

functions as SM0 and controls the operating mode. See Serial

Interface Modes, Table 10.

When FEDE is set to 1, this bit functions as a framing error flag

and will automatically be set to 1 when the incoming stop bit

has been received as a logic 0. When used as FE, this flag

must be cleared to 0 by software.

SM1

6

R/W

Serial Interface Mode Bit 1

See Serial Interface Modes, Table 10

SM2

5

R/W

Serial Interface Mode Bit 2

Mode 1 operation:

0 = Normal operation

1 = RXI flag not set if incoming stop is logic 0

Modes 2 and 3 operation:

0 = Multiprocessor mode disabled

1 = Multiprocessor mode enabled

REN

4

R/W

Reciever Enable

0 = Reciever enabled

1 = Reciever disabled

TB8

3

R/W

Transmit Data Bit 8

When in mode 2 or 3, this bit determines the state of the ninth

transmitted data bit. This bit is not used in mode 1.

RB8

2

R/W

Received Data Bit 8

When in mode 2 or 3, this bit indicates the state of the incoming

ninth data bit. In mode 1, this bit indicates the state of the stop

bit.

TI

1

R/W

Transmit Interrupt Flag

Set to 1 at the end of the last data bit transmitted.

TI must be cleared by software.

RI

0

R/W

Recieve Interrupt Flag

Set to 1 at the end of the stop bit sampling window when in

mode 1. Set to 1 at the end of the sampling window of the ninth

data bit when in mode 2 or 3.

RI must be cleared by software.