CEC1712 datasheet(85/338 Pages) MICROCHIP

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DS00003416C-page 85

CEC1712

5.6

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

5.6.1

POWER DOMAINS

5.6.2

CLOCK INPUTS

5.6.2.1

Basic Clocking

The basic clocking comes from a free-running Clock signal provided from the chip level.

5.6.2.2

System Tick Clocking

The System Tick clocking is controlled by a signal from chip-level logic. It is the 48MHz divided by the following:

-((PROCESSOR_CLOCK_DIVIDE)x2)+1

5.6.2.3

Debug JTAG Clocking

The Debug JTAG clocking comes from chip-level logic, which may multiplex or gate this clock. See Section 5.10,

"Debugger Access Support".

5.6.2.4

Trace Clocking

The Clock for the Trace interface is identical to the 48MHz input.

5.6.3

RESETS

The reset interface from the chip level is given below.

5.7

Interrupts

The ARM M4 Based Embedded Controller is equipped with an Interrupt Interface to respond to interrupts. These inputs

go to the IP’s NVIC block after a small amount of hardware processing to ensure their detection at varying clock rates.

See Figure 5-1, "ARM M4 Based Embedded Controller I/O Block Diagram".

As shown in Figure 5-1, an Interrupt Aggregator block may exist at the chip level, to allow multiple related interrupts to

be grouped onto the same NVIC input, and so allowing them to be serviced using the same vector. This may allow the

same interrupt handler to be invoked for a group of related interrupt inputs. It may also be used to expand the total num-

ber of interrupt inputs that can be serviced.

The NMI (Non-Maskable Interrupt) connection is tied off and not used.

5.7.1

NVIC INTERRUPT INTERFACE

The NVIC interrupt unit can be wired to up to 240 interrupt inputs from the chip level. The interrupts that are actually

connected from the chip level are defined in the Interrupt section.

All NVIC interrupt inputs can be programmed as either pulse or level triggered. They can also be individually masked,

and individually assigned to their own hardware-managed priority level.

TABLE 5-1:

POWER SOURCES

Name

Description

VTR_CORE

The ARM M4 Based Embedded Controller is powered by VTR_CORE.

TABLE 5-2:

CLOCK INPUTS

Name

Description

48MHz

The clock source to the EC. Division of the clock rate is determined by

the PROCESSOR_CLOCK_DIVIDE field in the Processor Clock Control

TABLE 5-3:

RESET SIGNALS

Name

Description

RESET_EC

The ARM M4 Based Embedded Controller is reset by RESET_EC.

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