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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CEC1712 датащи(PDF) 76 Page - Microchip Technology |
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CEC1712 датащи(HTML) 76 Page - Microchip Technology |
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76 / 338 page  CEC1712 DS00003416C-page 76 2020-2021 Microchip Technology Inc. 4.9.5 PROCESSOR CLOCK CONTROL REGISTER 4.9.6 SLOW CLOCK CONTROL REGISTER 4.9.7 OSCILLATOR ID REGISTER Offset 04h Bits Description Type Default Reset Event 31:8 Reserved RES - - 7:0 PROCESSOR_CLOCK_DIVIDE The following list shows examples of settings for this field and the resulting EC clock rate. 48=divide the 48MHz clock by 48 (1MHz processor clock) 16=divide the 48MHz clock by 16 (4MHz processor clock) 4=divide the 48MHz clock by 4 (12MHz processor clock) 3=divide the 48MHz clock by 3 (16MHz processor clock) 1=divide the 48MHz clock by 1 (48MHz processor clock) No other values are supported. R/W 4h RESET _SYS Offset 08h Bits Description Type Default Reset Event 31:10 Reserved RES - - 9:0 SLOW_CLOCK_DIVIDE Configures the 100KHz clock domain. n=Divide by n 0=Clock off The default setting is for 100KHz. R/W 1E0h RESET _SYS Offset 0Ch Bits Description Type Default Reset Event 31:9 Reserved RES - - 8 PLL_LOCK Phase Lock Loop Lock Status R0h RESET _SYS 7:0 TEST R N/A RESET _SYS |
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