CEC1712 datasheet(72/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 72

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The following table defines a block’s power management protocol:

A wake event clears all SLEEP_ENABLE bits momentarily, and then returns the SLEEP_ENABLE bits back to their orig-

inal state. The block that needs to respond to the wake event will do so.

The Sleep Enable, Clock Required and Reset Enable Registers are defined in Section 4.8.

4.7.2

CONFIGURING THE CHIP’S SLEEP STATES

The chip supports two sleep states: LIGHT SLEEP and HEAVY SLEEP. The chip will enter one of these two sleep states

only when all the blocks have been commanded to sleep and none of them require a 48MHz clock source (i.e., all

CLOCK_REQUIRED status bits are 0), and the processor has executed its sleep instruction. These sleep states must

be selected by firmware via the System Sleep Control bits implemented in the System Sleep Control Register prior to

issuing the sleep instruction. Table 4-9, "System Sleep Modes" defines each of these sleep states.

There are two ways to command the chip blocks to enter sleep.

Assert the SLEEP_ALL bit located in the System Sleep Control Register

Assert all the individual block sleep enable bits

Blocks will only enter sleep after their sleep signal is asserted and they no longer require the 48MHz source. Each block

has a corresponding clock required status bit indicating when the block has entered sleep. The general operation is that

a block will keep the 48MHz clock source on until it completes its current transaction. Once the block has completed its

work, it deasserts its clock required signal. Blocks like timers, PWMs, etc. will de-assert their clock required signals

immediately. See the individual block Low Power Mode sections to determine how each individual block enters sleep.

4.7.3

DETERMINING WHEN THE CHIP IS SLEEPING

The TST_CLK_OUT pin can be used to verify the chip’s clock has stopped, which indicates the device is in LIGHT

SLEEP or HEAVY SLEEP, as determined by the System Sleep Control Register. If the clock is toggling the chip is in the

full on running state. if the clock is not toggling the chip has entered the programmed sleep state.

4.7.4

WAKING THE CHIP FROM SLEEPING STATE

The chip will remain in the configured sleep state until it detects either a wake event or a full VTR_CORE POR. A wake

event occurs when a wake-capable interrupt is enabled and triggered. Interrupts that are not wake-capable cannot occur

while the system is in LIGHT SLEEP or HEAVY SLEEP.

In LIGHT SLEEP, the 48MHz clock domain is gated off, but the 48 MHz PLL remains operational and locked to the

32KHz clock domain. On wake, the PLL output is ungated and the 48MHz clock domain starts immediately, with the

PLL_LOCK bit in the Oscillator ID Register set to ‘1’. Any device that requires an accurate clock, such as a UART, may

be used immediately on wake.

TABLE 4-7:

POWER MANAGEMENT PROTOCOL

Power State

SLEEP_ENABLE CLOCK_REQUIRED

Description

Normal operation

Low

Block is idle and NOT requesting clocks. The block

gates its own internal clock.

Normal operation

Low

High

Block is NOT idle and requests clocks.

Request sleep

Rising Edge

Low

Block is IDLE and enters sleep mode immediately. The

block gates its own internal clock. The block cannot

request clocks again until SLEEP_ENABLE goes low.

Request sleep

Rising Edge

High then Low

Block is not IDLE and will stop requesting clocks and

enter sleep when it finishes what it is doing. This delay

is block specific, but should be less than 1 ms. The

block gates its own internal clock. After driving

CLOCK_REQUIRED low, the block cannot request

clocks again until SLEEP_ENABLE goes low.

High

less of SLEEP_ENABLE. Therefore the block ungates

its internal clock and drives CLOCK_REQUIRED high

during the access. The block will regate its internal

clock and drive CLOCK_REQUIRED low when the

access is done.

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