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CEC1712

DS00003416C-page 80

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5.0

ARM M4 BASED EMBEDDED CONTROLLER

5.1

Introduction

This chapter contains a description of the ARM M4 Embedded Controller (EC).

The EC is built around an ARM® Cortex®-M4 Processor provided by Arm Ltd. (the “ARM M4 IP”). The ARM Cortex®

M4 is a full-featured 32-bit embedded processor, implementing the ARMv7-M THUMB instruction set in hardware.

The ARM M4 IP is configured as a Von Neumann, Byte-Addressable, Little-Endian architecture. It provides a single uni-

fied 32-bit byte-level address, for a total direct addressing space of 4GByte. It has multiple bus interfaces, but these

express priorities of access to the chip-level resources (Instruction Fetch vs. Data RAM vs. others), and they do not

represent separate addressing spaces.

The ARM M4 is configured as follows.

• Little-Endian byte ordering is selected at all times

• Bit Banding is included for efficient bit-level access

• Debug features are included at “Ex+” level, defined as follows:

- DWT Unit provides 4 Data Watchpoint comparators and Execution Monitoring

• Trace features are included at “Full” level, defined as follows:

- DWT for reporting breakpoints and watchpoints

- ITM for profiling and to timestamp and output messages from instrumented firmware builds

- ETM for instruction tracing, and for enhanced reporting of Core and DWT events

- The ARM-defined HTM trace feature is not included

• NVIC Interrupt controller with 8 priority levels and up to 240 individually-vectored interrupt inputs

- A Microchip-defined Interrupt Aggregator function (at chip level) may be used to group multiple interrupts onto

single NVIC inputs

- The ARM-defined WIC feature is not included. The Microchip Interrupt Aggregator function (at chip level)

provides Wake control

• Single entry Write Buffer is incorporated

5.2

References

ARM Limited: Cortex®-M4 Technical Reference Manual, DDI0439C, 29 June 2010

ARM Limited: ARM®v7-M Architecture Reference Manual, DDI0403D, November 2010

NOTE: Filename DDI0403D_arm_architecture_v7m_reference_manual_errata_markup_1_0.pdf

ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification, IHI0048A, September

2008

ARM Limited: AMBA® Specification (Rev 2.0), IHI0011A, 13 May 1999

ARM Limited: AMBA® 3 AHB-Lite Protocol Specification, IHI0033A, 6 June 2006

ARM Limited: AMBA® 3 ATB Protocol Specification, IHI0032A, 19 June 2006

ARM Limited: Cortex-M™ System Design Kit Technical Reference Manual, DDI0479B, 16 June 2011

ARM Limited: CoreSight™ v1.0 Architecture Specification, IHI0029B, 24 March 2005

10. ARM Limited: CoreSight™ Components Technical Reference Manual, DDI0314H, 10 July 2009

11. ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006

12. ARM Limited: ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement, DSA09-PRDC-008772,

17 August 2009

13. ARM Limited: Embedded Trace Macrocell™ (ETMv1.0 to ETMv3.5) Architecture Specification, IHI0014Q, 23

September 2011

14. ARM Limited: CoreSight™ ETM™-M4 Technical Reference Manual, DDI0440C, 29 June 2010

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