AM79C978AVCW datasheet(73/256 Pages) AMD

73 / 256 page

Am79C978A

exchange allows both devices at either end of the link

to take maximum advantage of their respective

shared abilities.

The Am79C978A device implements the transmit and

receive Auto-Negotiation algorithm as defined in IEEE

802.3u, Section 28. The Auto-Negotiation algorithm

uses a burst of link pulses called Fast Link Pulses

(FLPs). The burst of link pulses are spaced between

55 and 140 µs so as to be ignored by the standard

10BASE-T algorithm. The FLP burst conveys informa-

tion about the abilities of the sending device. The re-

ceiver can accept and decode an FLP burst to learn

the abilities of the sending device. The link pulses

transmitted conform to the standard 10BASE-T tem-

plate. The device can perform auto-negotiation with

reverse polarity link pulses.

The Am79C978A device uses the Auto-Negotiation

algorithm to select the type connection to be estab-

lished according to the following priority: 10BASE-T

full duplex, then 10BASE-T half-duplex. See Table 12.

The Auto-Negotiation algorithm is initiated by the fol-

lowing events: Auto-Negotiation enable bit is set, hard-

ware reset, soft reset, transition to link fail state (when

Auto-Negotiation enable bit is set), or Auto-Negotiation

restart bit is set. The result of the Auto-Negotiation pro-

cess can be read from the status register (Summary

Status Register, TBR24).

By defa u lt , t h e lin k pa r t ne r m u st be at lea s t

10BASE-T half-duplex capable. The Am79C978A

controller can automatically negotiate with the net-

work and yield the highest performance possible

without software suppor t. See the Network Por t

Manager section for more details.

Auto-Negotiation goes further by providing a message-

based communication scheme called Next Pages be-

fore connecting to the Link Partner. This feature is not

suppor ted in the Am79C978A device unless the

DANAS (BCR32, bit 10) is selected.

Soft Reset Function

The PHY Control Register (TBR0) incorporates the soft

reset function (bit 15). It is a read/write register and is

self-clearing. Writing a 1 to this bit causes a soft reset.

When read, the register returns a 1 if the soft reset is

still being performed; otherwise, it is cleared to 0. Note

that the register can be polled to verify that the soft

reset has terminated. Under normal operating condi-

tions, soft reset will be finished in 150 clock cycles.

Soft reset only resets the 10BASE-T PHY unit regis-

ters to default values (some register bits retain their

previous values). Refer to the individual registers for

values after a soft reset. Soft reset does not reset the

management interface.

Table 12.

Auto-Negotiation Capabilities

Network Speed

Physical Network Type

20 Mbps

10BASE-T, Full Duplex

10 Mbps

10BASE-T, Half Duplex

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