AM79C978AVCW datasheet(49/256 Pages) AMD

49 / 256 page

Am79C978A

Whenever the Am79C978A controller is the current bus

master and a data parity error occurs, SINT (CSR5, bit

11) will be set to 1. When SINT is set, INTA is asserted

if the enable bit SINTE (CSR5, bit 10) is set to 1. This

mechanism can be used to inform the driver of the sys-

tem error. The host can read the PCI Status register to

determine the exact cause of the interrupt. The setting

of SINT due to a data parity error is not dependent on

the setting of PERREN (PCI Command register, bit 6).

By default, a data parity error does not affect the

state of the MAC engine. TheAm79C978A control-

ler treats the data in all bus master transfers that

have a parity error as if nothing has happened. All

network activity continues.

Advanced Parity Error Handling

For all DMA cycles, the Am79C978A controller provides

a second, more advanced level of parity error handling.

This mode is enabled by setting APERREN (BCR20, bit

10) to 1. When APERREN is set to 1, the BPE bits (RMD1

and TMD1, bit 23) are used to indicate parity error in data

transfers to the receive and transmit buffers. Note that

since the advanced parity error handling uses an addi-

tional bit in the descriptor, SWSTYLE (BCR20, bits 7-0)

must be set to 2 or 3 to program the Am79C978A con-

troller to use 32-bit software structures. TheAm79C978A

controller will react in the following way when a data parity

error occurs:

n Initialization block read: STOP (CSR0, bit 2) is set

to 1 and causes a STOP_RESET of the device.

n Descriptor ring read: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to 1 to cause a STOP_RESET

of the device.

n Descriptor ring write: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to 1 to cause a STOP_RESET

of the device.

n Transmit buffer read: BPE (TMD1, bit 23) is set in

the current transmit descriptor. Any on-going net-

work transmission is terminated in an orderly se-

quence.

n Receive buffer write: BPE (RMD1, bit 23) is set in

the last receive descriptor associated with the frame.

Terminating on-going network transmission in an

order ly sequence means that if less than 512

bits have been transmitted onto the network, the

trans mi ss i on wi ll be ter m i nate d i mme dia t ely,

generating a runt packet.

If 512 bits or more have been transmitted, the mes-

sage will have the current FCS inverted and ap-

pended at the next byte boundary to guarantee an

FCS error is detected at the receiving station.

APERREN does not affect the reporting of address

parity errors or data parity errors that occur when the

Am79C978A controller is the target of the transfer.

Initialization Block DMA Transfers

During execution of the Am79C978A controller bus

master initialization procedure, the microcode will re-

peatedly request DMA transfers from the BIU. During

each of these initialization block DMA transfers, the

BIU will perform two data transfer cycles reading one

DWord per transfer and then it will relinquish the bus.

When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the ini-

tialization block is organized as 32-bit software struc-

tures), there are seven DWords to transfer during the

bus master initialization procedure, so four bus mas-

tership periods are needed in order to complete the

initialization sequence. Note that the last DWord

transfer of the last bus mastership period of the initial-

ization sequence accesses an unneeded location.

Data from this transfer is discarded internally. When

SSIZE32 is cleared to 0 (i.e., the initialization block is

organized as 16-bit software structures), then three

bus mastership periods are needed to complete the

initialization sequence.

The Am79C978A device supports two transfer modes

for reading the initialization block: non-burst and burst

mode, with burst mode being the preferred mode

when the Am79C978A controller is used in a PCI bus

application. See Figure 25 and Figure 26.

When BREADE is cleared to 0 (BCR18, bit 6), all

initialization block read transfers will be executed in

non-burst mode. There is a new address phase for

every data phase. FRAME will be dropped between

the two transfers. The two phases within a bus mas-

tership period will have addresses of ascending

contiguous order.

When BREADE is set to 1 (BCR18, bit 6), all initializa-

tion block read transfers will be executed in burst

mode. AD[1:0] will be 0 during the address phase indi-

cating a linear burst order.

AM79C978AVCW датащи(PDF) 49 Page - Advanced Micro Devices

AM79C978AVCW датащи(HTML) 49 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL