AM79C978AVCW datasheet(70/256 Pages) AMD

70 / 256 page

Am79C978A

Figure 36.

IEEE 802.3 Frame and Length Field Transmission Order

The receive FIFO will delete any frame that is com-

posed of fewer than 64 bytes provided that the Runt

Packet Accept (RPA bit in CSR124) feature has not

been enabled and the network interface is operating

in half-duplex mode, or the full-duplex Runt Packet

Accept Disable bit (FDRPAD, BCR9, bit 2) is set.

This criterion will be met regardless of whether the

receive frame was the first (or only) frame in the

FIFO or if the receive frame was queued behind a

previously received message.

Abnormal network conditions include:

n FCS errors

n Late collision

Host related receive exception conditions include

MISS, BUFF, and OFLO. These are described in the

Buffer Management Unit section.

Loopback Operation

Loopback is a mode of operation intended for system

diagnostics. In this mode, the transmitter and receiver

are both operating at the same time so that the

Am79C978A controller receives its own transmissions.

The Am79C978A controller provides two basic types of

loopback. In internal loopback mode, the transmitted

data is looped ba ck to the receiver in side th e

Am79C978A controller without actually transmitting

any data to the external network. The receiver will

move the received data to the next receive buffer,

where it can be examined by software. Alternatively, in

external loopback mode, data can be transmitted to

and received from the external network.

Refer to Table 30 for various bit settings required for

Loopback modes.

The external loopback requires a two-step operation.

The internal PHY must be placed into a loopback mode

by writing to the PHY Control Register (BCR33,

BCR34). Then, the Am79C978A controller must be

placed into an external loopback mode by setting the

Loop bits.

Miscellaneous Loopback Features

All transmit and receive function programming, such as

automatic transmit padding and receive pad stripping,

operates identically in loopback as in normal operation.

Runt Packet Accept is internally enabled (RPA bit in

CSR124 is not affected) when any loopback mode is in-

voked. This is to be backwards compatible to the

C-LANCE (Am79C90) software.

Since the Am79C978A controller has two FCS genera-

tors, there are no more restrictions on FCS generation

or checking, or on testing multicast address detection

as they exist in the half-duplex PCnet family devices

and in the C-LANCE. On receive, the Am79C978A

controller now provides true FCS status. The descriptor

for a frame with an FCS error will have the FCS bit

(RMD1, bit 27) set to 1. The FCS generator on the

transmit side can still be disabled by setting DXMTFCS

(CSR15, bit 3) to 1.

Preamble

1010....1010

SFD

10101011

Destination

Address

Source

Address

Length

LLC

Data

Pad

FCS

Bytes

46 – 1500

Bytes

Bits

Start of Frame

at Time = 0

Increasing Time

Bit

Most

Significant

Byte

Least

Significant

Byte

1 – 1500

Bytes

45 – 0

Bytes

22399A-39

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