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AT25SF321 датащи(PDF) 23 Page - Dialog Semiconductor

номер детали AT25SF321
подробное описание детали  32-Mbit, 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-IO Support
PDF  48 Pages
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AT25SF321
DS-25SF321–047F–8/2017
Table 8-2.
Memory Array Protection with CMP=1
As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the Protection can be
locked from updates by using the WP pin (see “Protected States and the Write Protect Pin” on page 22 for more details).
8.4
Protected States and the Write Protect Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array.
Instead, the WP pin, is used to control the hardware locking mechanism of the device.
If the WP pin is permanently connected to GND, then the protection bits cannot be changed.
Protection Bits
Memory Content
SEC
TB
BP2
BP1
BP0
Address Range
Portion
X
X
0
0
0
000000h-3FFFFFh
All
0
0
0
0
1
000000h-3EFFFFh
Lower 63/64
0
0
0
1
0
000000h-3DFFFFh
Lower 31/32
0
0
0
1
1
000000h-3BFFFFh
Lower 15/16
0
0
1
0
0
000000h-37FFFFh
Lower 7/8
0
0
1
0
1
000000h-2FFFFFh
Lower 3/4
0
0
1
1
0
000000h-1FFFFFh
Lower 1/2
0
1
0
0
1
010000h-3FFFFFh
Upper 63/64
0
1
0
1
0
020000h-3FFFFFh
Upper 31/32
0
1
0
1
1
040000h-3FFFFFh
Upper 15/16
0
1
1
0
0
080000h-3FFFFFh
Upper 7/8
0
1
1
0
1
100000h-3FFFFFh
Upper 3/4
0
1
1
1
0
200000h-3FFFFFh
Upper 1/2
X
X
1
1
1
NONE
NONE
1
0
0
0
1
000000h-3FEFFFh
Lower 1023/1024
1
0
0
1
0
000000h-3FDFFFh
Lower 511/512
1
0
0
1
1
000000h-3FBFFFh
Lower 255/256
1
0
1
0
X
000000h-3F7FFFh
Lower 127/128
1
0
1
1
0
000000h-3F7FFFh
Lower 127/128
1
1
0
0
1
001000h-3FFFFFh
Upper 1023/1024
1
1
0
1
0
002000h-3FFFFFh
Upper 511/512
1
1
0
1
1
004000h-3FFFFFh
Upper 255/256
1
1
1
0
X
008000h-3FFFFFh
Upper 127/128
1
1
1
1
0
008000h-3FFFFFh
Upper 127/128



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