AT25SF321 datasheet(4/48 Pages) DIALOG

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AT25SF321

DS-25SF321–047F–8/2017

SO (I/O1)

SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin

is always clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in

conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every

falling edge of SCK

To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as

the SO pin unless specifically addressing the Dual-I/O modes in which case it will be

referenced as I/O1

The SO pin will be in a high-impedance state whenever the device is deselected (CS is

deasserted).

Input/Output

(I/O2)

WRITE PROTECT: The WP pin controls the hardware locking feature of the device.

With the Quad-Input Byte/Page Program command, the WP pin becomes an input pin (I/O2)

and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every rising

edge of SCK. With the Quad-Output Read commands, the WP Pin becomes an output pin

(I/O2) in conjunction with other pins to allow four bits of data on (I/O33-0) to be clocked in on

every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the WP (I/O2) pin will be referenced as

the WP pin unless specifically addressing the Quad-I/O modes in which case it will be

referenced as I/O2

The WP pin is internally pulled-high and may be left floating if hardware controlled protection

will not be used. However, it is recommended that the WP pin also be externally connected

to VCC whenever possible.

Input/Output

HOLD

(I/O3)

HOLD: The HOLD pin is used to temporarily pause serial communication without

deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK

pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold

condition to start. A Hold condition pauses serial communication only and does not have an

effect on internally self-timed operations such as a program or erase cycle. Please refer to

“Hold Function” on page 34 for additional details on the Hold operation.

With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin

(I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to be clocked in on every

rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin becomes an

output pin (I/O3) in conjunction with other pins to allow four bits of data on (I/O33-0) to be

clocked in on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin will be referenced

as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be

referenced as I/O3

The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be

used. However, it is recommended that the HOLD pin also be externally connected to VCC

whenever possible.

Input/Output

VCC

DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.

Operations at invalid VCC voltages may produce spurious results and should not be

attempted.

Power

GND

GROUND: The ground reference for the power supply. GND should be connected to the

system ground.

Power

Table 1-1.

Pin Descriptions (Continued)

Symbol

Name and Function

Asserted

State

Type

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