DSPIC33EP128GS708 datasheet(56/484 Pages) MICROCHIP

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dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 56

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4.6.3

MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions, and the DSP accumulator class

of instructions, provide a greater degree of address-

ing flexibility than other instructions. In addition to the

addressing

modes

supported

most

MCU

instructions, move and accumulator instructions also

support Register Indirect with Register Offset

Addressing mode, also referred to as Register Indexed

mode.

In summary, the following addressing modes are

supported by move and accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-Bit Literal

• 16-Bit Literal

4.6.4

MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred

to as MAC instructions, use a simplified set of addressing

modes to allow the user application to effectively

manipulate the Data Pointers through register indirect

tables.

The two-source operand prefetch registers must be

members of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 are always directed to the X RAGU,

and W10 and W11 are always directed to the Y AGU.

The Effective Addresses generated (before and after

modification) must therefore, be valid addresses within

X Data Space for W8 and W9, and Y Data Space for

W10 and W11.

In summary, the following addressing modes are

supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-Modified by 2

• Register Indirect Post-Modified by 4

• Register Indirect Post-Modified by 6

• Register Indirect with Register Offset (Indexed)

4.6.5

OTHER INSTRUCTIONS

Besides the addressing modes outlined previously,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit

signed literals to specify the branch destination directly,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, such as ULNK, the

source of an operand or result is implied by the opcode

itself. Certain operations, such as a NOP, do not have

any operands.

Note:

For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Register Offset) field is

shared by both source and destination (but

typically only used by one).

Note:

Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing modes.

Note:

Addressing mode is available only for W9

(in X space) and W11 (in Y space).

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