DSPIC33EP128GS708 datasheet(18/484 Pages) MICROCHIP

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dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 18

 2016-2018 Microchip Technology Inc.

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTION

2.2.1

TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits, including DSCs, to supply a local

power source. The value of the tank capacitor should

be determined based on the trace resistance that con-

nects the power supply source to the device and the

maximum current drawn by the device in the applica-

tion. In other words, select the tank capacitor so that it

meets the acceptable voltage sag at the device. Typical

values range from 4.7 µF to 47 µF.

2.3

CPU Logic Filter Capacitor

Connection (VCAP)

A low-ESR (< 0.5Ω) capacitor is required on the VCAP

pin, which is used to stabilize the voltage regulator

output voltage. The VCAP pin must not be connected to

VDD and must have a capacitor greater than 4.7 µF

(10 µF is recommended), 16V connected to ground. The

type can be ceramic or tantalum. See Section 30.0

“Electrical Characteristics” for additional information.

The placement of this capacitor should be close to the

VCAP pin. It is recommended that the trace length not

exceed one-quarter inch (6 mm). See Section 27.4

“On-Chip Voltage Regulator” for details.

2.4

Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions:

• Device Reset

• Device Programming and Debugging.

During device programming and debugging, the

resistance and capacitance that can be added to the

pin must be considered. Device programmers and

debuggers drive the MCLR pin. Consequently,

specific voltage levels (VIH and VIL) and fast signal

transitions must not be adversely affected. Therefore,

specific values of R and C will need to be adjusted

based on the application and PCB requirements.

For example, as shown in Figure 2-2, it is recom-

mended that the capacitor, C, be isolated from the

MCLR pin during programming and debugging

operations.

Place the components as shown in Figure 2-2, within

one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS

Note 1:

As an option, instead of a hard-wired connection, an

inductor (L1) can be substituted between VDD and

AVDD to improve ADC noise rejection. The inductor

impedance should be less than 1

 and the inductor

capacity greater than 10 mA.

Where:

FCNV

--------------

 LC



-----------------------

fC



----------------------



 2

(i.e., ADC Conversion Rate/2)

dsPIC33EP

VDD

VSS

VDD

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

VDD

MCLR

0.1 µF

Ceramic

L1(1)

10 µF

Tantalum

R1(2)

R(1)

VDD

MCLR

dsPIC33EP

Note 1: R

 10 k is recommended. A suggested

starting value is 10 k

. Ensure that the

MCLR pin VIH and VIL specifications are met.

2: R1

 470 will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

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