DS1925 datasheet(8/46 Pages) MAXIM

8 / 46 page

Parasite Power

The block diagram (Figure 1) shows the parasite-powered

circuitry. This circuitry “steals” power whenever the I/O

input is high. I/O provides sufficient power as long as

the specified timing and voltage requirements are met.

The advantage of parasite power is that if the battery is

exhausted for any reason, the ROM and data log may still

be read.

64-Bit Unique ROM

Each DS1925 contains a unique ROM code that is 64 bits

long. The first 8 bits are a 1-Wire family code. The next

48 bits are a unique serial number. The last 8 bits are

a CRC of the first 56 bits. See Figure 3 for details. The

1-Wire CRC is generated using a polynomial generator

consisting of a shift register and XOR gates as shown in

Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional

information about the Maxim Integrated 1-Wire Cyclic

Redundancy Check (CRC) is available in Application Note

27: Understanding and Using Cyclic Redundancy Checks

with Maxim 1-Wire and iButton Products.

The shift register bits are initialized to 0. Then starting with

the least significant bit of the family code, one bit at a time

is shifted in. After the 8th bit of the family code has been

entered, then the serial number followed by the tempera-

ture range code is entered. After the range code has been

entered, the shift register contains the CRC value. Shifting

in the 8 bits of CRC returns the shift register to all 0s.

Clear Memory State

The DS1925 enters a clear memory state if it is new or if an

XPC Clear Memory (log) sequence is done. In this state,

some commands that enable the RTC take extra time the

first time they are called. The commands that could incur this

additional delay (tSRTC) are XPC Copy Scratchpad (99h),

XPC Forced Conversion (4Bh), XPC Start Mission (DDh),

and XPC Read Battery Voltage (33h). This is a one-time

delay when coming out of the clear memory state.

Note: Any DS1925 device that is in an unknown state should

be assumed to require the additional delay of tSRTC to

ensure proper operation until the device state is established

by command or query. Failure to do so may cause the

device to experience a power-on-reset or battery-fail event,

setting the BOR alarm flag and disabling device features.

Figure 3. 64-Bit Unique ROM

Figure 4. 1-Wire CRC Generator

DS1925

iButton High-Capacity Temperature Logger

with 122KB Data-Log Memory

www.maximintegrated.com

Maxim Integrated │ 8

8-BIT CRC CODE

48-BIT SERIAL NUMBER

8-BIT FAMILY CODE [53h]

MSB

LSB

MSB

LSB MSB

LSB

INPUT DATA

1st

STAGE

2nd

STAGE

3rd

STAGE

4th

STAGE

5th

STAGE

6th

STAGE

7th

STAGE

8th

STAGE

POLYNOMIAL = X8 + X5 + X4 + 1

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