ACE34AC04

4K I

VER 1.1

8

Memory Organization

To provide the greatest flexibility and backwards compatibility with the previous generations of SPD

devices, the ACE34AC04 memory organization is organized into two independent 2-Kbit memory arrays.

Each 2-Kbit (256-byte) section is internally organized into two independent quadrants of 128 bytes with

each quadrant comprised of eight pages of 16 bytes. Including both memory sections, there are four

128-byte quadrants totaling 512 bytes.

Set Page Address and Read Page Address Commands

The ACE34AC04 incorporates an innovative memory addressing technique that utilizes a Set desired half

of the memory enabled to perform Write and Read operations. Due to the requirement for A0 pin to be

driven to VHV, the SPA and the RPA commands are fully supported in a single DIMM (isolated DIMM) end

application or a single DIMM programming station only. If SPA = 0, then the first-half or lower 256 bytes of

the Serial EEPROM is selected allowing access to Quadrant 0 and Quadrant 1. Alternately, if SPA = 1,

then the second-half or upper 256 bytes of the Serial EEPROM is selected allowing access to Quadrant 2

and Quadrant 3.

Table 3: SPA Setting and Memory Organization

Block

Set Page Address (SPA)

Memory Address Locations

Quadrant 0

0

00h to 7Fh

Quadrant 1

80h to FFh

Quadrant 2

1

00h to 7Fh

Quadrant 3

80h to FFh

Setting the Set Page Address (SPA) value selects the desired half of the EEPROM for performing Write or

Read operations. This is done by sending the SPA as seen in Figure 6-1. The SPA command sequence

requires the Master to transmit a Start condition followed by sending a control byte of ‘011011*0’ where

the ‘*’ in the bit 7 position will dictate which half of the EEPROM is being addressed. A ‘0’ in this position

(or 6Ch) is required to set the page address to the first half of the memory and a ‘1’ (or 6Eh) is necessary

to set the page address to the second half of the memory. After receiving the control byte, the

ACE34AC04 should return an ACK and the Master should follow by sending two data bytes of don’t care

values. The ACE34AC04 responds with a NACK to each of these two data bytes although the JEDEC

EE1004v specification allows for either an ACK or NACK response. The protocol is completed by the

Master sending a Stop condition to end the operation.

Figure 5: Set Page Address (SPA)