ACE34AC04

4K I

VER 1.1

5

(D)

Acknowledge

The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The

EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The

ACKNOWLEDGE signal occurs on the 9th serial clock after each word.

(E)

No-ACKNOWLEDGE (NACK)

When the ACE34AC04 is transmitting data to the Master, the Master can indicate that it is done

receiving data and wants to end the operation by sending a NACK response to the ACE34AC04

instead of an ACK response. This is accomplished by the Master outputting a Logic 1 during the

ACK/NACK clock cycle, at which point theACE34AC04 will release the SDA line so that the Master

can then generate a Stop condition.

(F)

Standby Mode

The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP

bit in read mode, or after completing a self-time internal programming operation.

Figure 1: Timing diagram for start and stop conditions

Figure 2: Timing diagram for output acknowledge