ACE34AC04

4K I

VER 1.1

4

Device Operation

The ACE34AC04 operates as a slave device and utilizes a simple 2-wire digital serial interface,

compatible with the I2C Fast-Mode Plus (I2C FM+) protocol, to communicate with a host controller,

commonly referred to as the bus Master. The Master initiates and controls all Read and Write operations

to the slave devices on the serial bus and both the Master and the slave devices can transmit and receive

data on the bus. The serial interface is comprised of just two signal lines: the Serial Clock (SCL) and the

Serial Data (SDA). The SCL pin is used to receive the clock signal from the Master, while the bidirectional

SDA pin is used to receive command and data information from the Master, as well as, to send data back

to the Master. Data is always latched into the ACE34AC04 on the rising edge of SCL and is always output

from the device on the falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike

suppression filters and Schmitt Triggers to minimize the effects of input spikes and bus noise. All

command and data information is transferred with the Most-Significant Bit (MSB) first. During the bus

communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has

been transferred, the receiving device must respond with either an acknowledge (ACK) or a no-

acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the

Master. Therefore, nine clock cycles are required for every one byte of data transferred. There are no

unused clock cycles during any Read or Write operation so there must not be any interruptions or breaks

in the data stream during each data byte transfer and ACK or NACK clock cycle. During data transfers,

data on the SDA pin must only change while SCL is low, and the data must remain stable while SCL is

high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur.

Start and Stop conditions are used to initiate and end all serial bus communication between the Master

and the slave devices. The number of data bytes transferred between a Start and a Stop condition is not

limited and is determined by the Master. In order for the serial bus to be idle, both the SCL and SDA pins

must be in the Logic 1 state at the same time.

(A)

Serial Clock And Data Transitions

The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when

condition as described below.

(B)

Start Condition

With SCL ≥ VIH, a SDA transition from high to low is interpreted as a START condition. All valid

commands must begin with a START condition.

(C)

Stop Condition

With SCL ≥ VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read

or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after

a read command.

A STOP condition after page or byte write command will trigger the chip into the STANDBY mode

after the self- timed internal programming finish.